EN

Bit 0: AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase..

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

DATATYPE

Bits 1-2: Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

Allowed values:
0x0: B_0x0: None
0x1: B_0x1: Half-word (16-bit)
0x2: B_0x2: Byte (8-bit)
0x3: B_0x3: Bit

MODE

Bits 3-4: AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4..

Allowed values:
0x0: B_0x0: Mode 1: encryption
0x1: B_0x1: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
0x2: B_0x2: Mode 3: decryption
0x3: B_0x3: Mode 4: key derivation then single decryption

CHMOD1

Bits 5-6: Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

CCFC

Bit 7: Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: Reading the flag always returns zero..

Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Clear CCF

ERRC

Bit 8: Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: Reading the flag always returns zero..

Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Clear RDERR and WRERR flags

CCFIE

Bit 9: CCF interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set:.

Allowed values:
0x0: B_0x0: Disable (mask)
0x1: B_0x1: Enable

ERRIE

Bit 10: Error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set:.

Allowed values:
0x0: B_0x0: Disable (mask)
0x1: B_0x1: Enable

DMAINEN

Bit 11: DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended..

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

DMAOUTEN

Bit 12: DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended..

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

GCMPH

Bits 13-14: GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield)..

Allowed values:
0x0: B_0x0: Init phase
0x1: B_0x1: Header phase
0x2: B_0x2: Payload phase
0x3: B_0x3: Final phase

CHMOD2

Bit 16: Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

KEYSIZE

Bit 18: Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

Allowed values:
0x0: B_0x0: 128
0x1: B_0x1: 256

NPBLB

Bits 20-23: Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ....

Allowed values:
0x0: B_0x0: All bytes are valid (no padding)
0x1: B_0x1: Padding for one least-significant byte of last block
0xF: B_0xF: Padding for 15 least-significant bytes of last block

CCF

Bit 0: Computation completed flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1..

Allowed values:
0x0: B_0x0: Not completed
0x1: B_0x1: Completed

RDERR

Bit 1: Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected read returns zero..

Allowed values:
0x0: B_0x0: Not detected
0x1: B_0x1: Detected

WRERR

Bit 2: Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected write is ignored..

Allowed values:
0x0: B_0x0: Not detected
0x1: B_0x1: Detected

BUSY

Bit 3: Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process..

Allowed values:
0x0: B_0x0: Idle
0x1: B_0x1: Busy

DIN

Bits 0-31: Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the AES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext The data swap operation is described in page 499..

DOUT

Bits 0-31: Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the AES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext The data swap operation is described in page 499..

KEY

Bits 0-31: Cryptographic key, bits [31:0] This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key. Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key. The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details..

KEY

Bits 0-31: Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

KEY

Bits 0-31: Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

KEY

Bits 0-31: Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

IVI

Bits 0-31: Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled.

IVI

Bits 0-31: Initialization vector input, bits [63:32] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield..

IVI

Bits 0-31: Initialization vector input, bits [95:64] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield..

IVI

Bits 0-31: Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield..

KEY

Bits 0-31: Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

KEY

Bits 0-31: Cryptographic key, bits [191:160] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

KEY

Bits 0-31: Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

KEY

Bits 0-31: Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

DR

Bits 0-31: Data register bits.

IDR

Bits 0-31: General-purpose 32-bit data register bits.

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

Allowed values:
0x0: B_0x0: 32 bit polynomial
0x1: B_0x1: 16 bit polynomial
0x2: B_0x2: 8 bit polynomial
0x3: B_0x3: 7 bit polynomial

REV_IN

Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data.

Allowed values:
0x0: B_0x0: Bit order not affected
0x1: B_0x1: Bit reversal done by byte
0x2: B_0x2: Bit reversal done by half-word
0x3: B_0x3: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

Allowed values:
0x0: B_0x0: Bit order not affected
0x1: B_0x1: Bit-reversed output format

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

Bits 0-31: Programmable polynomial.

EN1

Bit 0: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1..

Allowed values:
0x0: B_0x0: DAC channel1 disabled
0x1: B_0x1: DAC channel1 enabled

TEN1

Bit 1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle..

Allowed values:
0x0: B_0x0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register
0x1: B_0x1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register

TSEL1

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0x0: B_0x0: SWTRIG1
0x1: B_0x1: dac_ch1_trg1
0x2: B_0x2: dac_ch1_trg2
0xF: B_0xF: dac_ch1_trg15

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0x0: B_0x0: wave generation disabled
0x1: B_0x1: Noise wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

DMAEN1

Bit 12: DAC channel1 DMA enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: DAC channel1 DMA mode disabled
0x1: B_0x1: DAC channel1 DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: DAC channel1 DMA Underrun Interrupt disabled
0x1: B_0x1: DAC channel1 DMA Underrun Interrupt enabled

CEN1

Bit 14: DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

Allowed values:
0x0: B_0x0: DAC channel1 in Normal operating mode
0x1: B_0x1: DAC channel1 in calibration mode

EN2

Bit 16: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. Note: These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 disabled
0x1: B_0x1: DAC channel2 enabled

TEN2

Bit 17: DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_pclk clock cycle later to the DAC_DOR2 register
0x1: B_0x1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_pclk clock cycles later to the DAC_DOR2 register

TSEL2

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: SWTRIG2
0x1: B_0x1: dac_ch2_trg1
0x2: B_0x2: dac_ch2_trg2
0xF: B_0xF: dac_ch2_trg15

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: wave generation disabled
0x1: B_0x1: Noise wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

DMAEN2

Bit 28: DAC channel2 DMA enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 DMA mode disabled
0x1: B_0x1: DAC channel2 DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 DMA underrun interrupt disabled
0x1: B_0x1: DAC channel2 DMA underrun interrupt enabled

CEN2

Bit 30: DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 in Normal operating mode
0x1: B_0x1: DAC channel2 in calibration mode

SWTRIG1

Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..

Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger

SWTRIG2

Bit 1: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1..

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2..

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2..

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DACC1DOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

DACC2DOR

Bits 0-11: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2..

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel1
0x1: B_0x1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG1

Bit 14: DAC channel1 calibration offset status This bit is set and cleared by hardware.

Allowed values:
0x0: B_0x0: calibration trimming value is lower than the offset correction value
0x1: B_0x1: calibration trimming value is equal or greater than the offset correction value

BWST1

Bit 15: DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization)..

Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel2
0x1: B_0x1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate).

CAL_FLAG2

Bit 30: DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: calibration trimming value is lower than the offset correction value
0x1: B_0x1: calibration trimming value is equal or greater than the offset correction value

BWST2

Bit 31: DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written

OTRIM1

Bits 0-4: DAC channel1 offset trimming value.

OTRIM2

Bits 16-20: DAC channel2 offset trimming value These bits are available only on dual-channel DACs. Refer to implementation..

MODE1

Bits 0-2: DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample & hold mode Note: This register can be modified only when EN1=0..

Allowed values:
0x0: B_0x0: DAC channel1 is connected to external pin with Buffer enabled
0x1: B_0x1: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x2: B_0x2: DAC channel1 is connected to external pin with Buffer disabled
0x3: B_0x3: DAC channel1 is connected to on chip peripherals with Buffer disabled
0x4: B_0x4: DAC channel1 is connected to external pin with Buffer enabled
0x5: B_0x5: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x6: B_0x6: DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled
0x7: B_0x7: DAC channel1 is connected to on chip peripherals with Buffer disabled

MODE2

Bits 16-18: DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel2 mode: DAC channel2 in Normal mode DAC channel2 in Sample and hold mode Note: This register can be modified only when EN2=0. Refer to for the availability of DAC channel2..

Allowed values:
0x0: B_0x0: DAC channel2 is connected to external pin with Buffer enabled
0x1: B_0x1: DAC channel2 is connected to external pin and to on chip peripherals with buffer enabled
0x2: B_0x2: DAC channel2 is connected to external pin with buffer disabled
0x3: B_0x3: DAC channel2 is connected to on chip peripherals with Buffer disabled
0x4: B_0x4: DAC channel2 is connected to external pin with Buffer enabled
0x5: B_0x5: DAC channel2 is connected to external pin and to on chip peripherals with Buffer enabled
0x6: B_0x6: DAC channel2 is connected to external pin and to on chip peripherals with Buffer disabled
0x7: B_0x7: DAC channel2 is connected to on chip peripherals with Buffer disabled

TSAMPLE1

Bits 0-9: DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1=1, the write operation is ignored..

TSAMPLE2

Bits 0-9: DAC channel2 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is low, if BWST2=1, the write operation is ignored..

THOLD1

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode) Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN1=0..

THOLD2

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode). Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation..

TREFRESH1

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN1=0..

TREFRESH2

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation..

DEV_ID

Bits 0-11: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

DBG_STOP

Bit 1: Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration..

Allowed values:
0x0: B_0x0: All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator.
0x1: B_0x1: FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events.

DBG_STANDBY

Bit 2: Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode..

Allowed values:
0x0: B_0x0: Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby)
0x1: B_0x1: Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset.

DBG_TIM2_STOP

Bit 0: Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM3_STOP

Bit 1: Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM6_STOP

Bit 4: Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM7_STOP

Bit 5: Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_RTC_STOP

Bit 10: Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_WWDG_STOP

Bit 11: Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_IWDG_STOP

Bit 12: Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout when core is halted.

Allowed values:
0x0: B_0x0: Same behavior as in normal mode
0x1: B_0x1: The SMBUS timeout is frozen

DBG_LPTIM2_STOP

Bit 30: Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_LPTIM1_STOP

Bit 31: Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM1_STOP

Bit 11: Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM14_STOP

Bit 15: Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM15_STOP

Bit 16: Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx..

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM16_STOP

Bit 17: Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM17_STOP

Bit 18: Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

GIF1

Bit 0: Channel 1 global interrupt flag.

TCIF1

Bit 1: Channel 1 transfer complete flag.

HTIF1

Bit 2: Channel 1 half transfer flag.

TEIF1

Bit 3: Channel 1 transfer error flag.

GIF2

Bit 4: Channel 2 global interrupt flag.

TCIF2

Bit 5: Channel 2 transfer complete flag.

HTIF2

Bit 6: Channel 2 half transfer flag.

TEIF2

Bit 7: Channel 2 transfer error flag.

GIF3

Bit 8: Channel 3 global interrupt flag.

TCIF3

Bit 9: Channel 3 transfer complete flag.

HTIF3

Bit 10: Channel 3 half transfer flag.

TEIF3

Bit 11: Channel 3 transfer error flag.

GIF4

Bit 12: Channel 4 global interrupt flag.

TCIF4

Bit 13: Channel 4 transfer complete flag.

HTIF4

Bit 14: Channel 4 half transfer flag.

TEIF4

Bit 15: Channel 4 transfer error flag.

GIF5

Bit 16: Channel 5 global interrupt flag.

TCIF5

Bit 17: Channel 5 transfer complete flag.

HTIF5

Bit 18: Channel 5 half transfer flag.

TEIF5

Bit 19: Channel 5 transfer error flag.

GIF6

Bit 20: Channel 6 global interrupt flag.

TCIF6

Bit 21: Channel 6 transfer complete flag.

HTIF6

Bit 22: Channel 6 half transfer flag.

TEIF6

Bit 23: Channel 6 transfer error flag.

GIF7

Bit 24: Channel 7 global interrupt flag.

TCIF7

Bit 25: Channel 7 transfer complete flag.

HTIF7

Bit 26: Channel 7 half transfer flag.

TEIF7

Bit 27: Channel 7 transfer error flag.

CGIF1

Bit 0: Clear channel 1 global interrupt flag.

CTCIF1

Bit 1: Clear channel 1 transfer complete flag.

CHTIF1

Bit 2: Clear channel 1 half transfer flag.

CTEIF1

Bit 3: Clear channel 1 transfer error flag.

CGIF2

Bit 4: Clear channel 2 global interrupt flag.

CTCIF2

Bit 5: Clear channel 2 transfer complete flag.

CHTIF2

Bit 6: Clear channel 2 half transfer flag.

CTEIF2

Bit 7: Clear channel 2 transfer error flag.

CGIF3

Bit 8: Clear channel 3 global interrupt flag.

CTCIF3

Bit 9: Clear channel 3 transfer complete flag.

CHTIF3

Bit 10: Clear channel 3 half transfer flag.

CTEIF3

Bit 11: Clear channel 3 transfer error flag.

CGIF4

Bit 12: Clear channel 4 global interrupt flag.

CTCIF4

Bit 13: Clear channel 4 transfer complete flag.

CHTIF4

Bit 14: Clear channel 4 half transfer flag.

CTEIF15

Bit 15: Clear channel 4 transfer error flag.

CGIF5

Bit 16: Clear channel 5 global interrupt flag.

CTCIF5

Bit 17: Clear channel 5 transfer complete flag.

CHTIF5

Bit 18: Clear channel 5 half transfer flag.

CTEIF5

Bit 19: Clear channel 5 transfer error flag.

CGIF6

Bit 20: Clear channel 6 global interrupt flag.

CTCIF6

Bit 21: Clear channel 6 transfer complete flag.

CHTIF6

Bit 22: Clear channel 6 half transfer flag.

CTEIF6

Bit 23: Clear channel 6 transfer error flag.

CGIF7

Bit 24: Clear channel 7 global interrupt flag.

CTCIF7

Bit 25: Clear channel 7 transfer complete flag.

CHTIF7

Bit 26: Clear channel 7 half transfer flag.

CTEIF7

Bit 27: Clear channel 7 transfer error flag.

PA

Bits 0-31: Peripheral address.

MA

Bits 0-31: Memory address.

GIF1

Bit 0: Channel 1 global interrupt flag.

TCIF1

Bit 1: Channel 1 transfer complete flag.

HTIF1

Bit 2: Channel 1 half transfer flag.

TEIF1

Bit 3: Channel 1 transfer error flag.

GIF2

Bit 4: Channel 2 global interrupt flag.

TCIF2

Bit 5: Channel 2 transfer complete flag.

HTIF2

Bit 6: Channel 2 half transfer flag.

TEIF2

Bit 7: Channel 2 transfer error flag.

GIF3

Bit 8: Channel 3 global interrupt flag.

TCIF3

Bit 9: Channel 3 transfer complete flag.

HTIF3

Bit 10: Channel 3 half transfer flag.

TEIF3

Bit 11: Channel 3 transfer error flag.

GIF4

Bit 12: Channel 4 global interrupt flag.

TCIF4

Bit 13: Channel 4 transfer complete flag.

HTIF4

Bit 14: Channel 4 half transfer flag.

TEIF4

Bit 15: Channel 4 transfer error flag.

GIF5

Bit 16: Channel 5 global interrupt flag.

TCIF5

Bit 17: Channel 5 transfer complete flag.

HTIF5

Bit 18: Channel 5 half transfer flag.

TEIF5

Bit 19: Channel 5 transfer error flag.

CGIF1

Bit 0: Clear channel 1 global interrupt flag.

CTCIF1

Bit 1: Clear channel 1 transfer complete flag.

CHTIF1

Bit 2: Clear channel 1 half transfer flag.

CTEIF1

Bit 3: Clear channel 1 transfer error flag.

CGIF2

Bit 4: Clear channel 2 global interrupt flag.

CTCIF2

Bit 5: Clear channel 2 transfer complete flag.

CHTIF2

Bit 6: Clear channel 2 half transfer flag.

CTEIF2

Bit 7: Clear channel 2 transfer error flag.

CGIF3

Bit 8: Clear channel 3 global interrupt flag.

CTCIF3

Bit 9: Clear channel 3 transfer complete flag.

CHTIF3

Bit 10: Clear channel 3 half transfer flag.

CTEIF3

Bit 11: Clear channel 3 transfer error flag.

CGIF4

Bit 12: Clear channel 4 global interrupt flag.

CTCIF4

Bit 13: Clear channel 4 transfer complete flag.

CHTIF4

Bit 14: Clear channel 4 half transfer flag.

CTEIF15

Bit 15: Clear channel 4 transfer error flag.

CGIF5

Bit 16: Clear channel 5 global interrupt flag.

CTCIF5

Bit 17: Clear channel 5 transfer complete flag.

CHTIF5

Bit 18: Clear channel 5 half transfer flag.

CTEIF5

Bit 19: Clear channel 5 transfer error flag.

PA

Bits 0-31: Peripheral address.

MA

Bits 0-31: Memory address.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

SOF0

Bit 0: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF1

Bit 1: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF2

Bit 2: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF3

Bit 3: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF4

Bit 4: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF5

Bit 5: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF6

Bit 6: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

CSOF0

Bit 0: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF1

Bit 1: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF2

Bit 2: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF3

Bit 3: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF4

Bit 4: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF5

Bit 5: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF6

Bit 6: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt on a trigger overrun event occurrence is disabled
0x1: B_0x1: interrupt on a trigger overrun event occurrence is enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0x0: B_0x0: DMA request generator channel x disabled
0x1: B_0x1: DMA request generator channel x enabled

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

Allowed values:
0x0: B_0x0: no event. I.e. none trigger detection nor generation.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge