Overall: 1778/3431 fields covered

AES

0x40026000: Advanced Encryption Standard

17/40 fields covered. Toggle Registers.

AES_CR

AES control register

Offset: 0x0, reset: 0x00000000, access: Unspecified

12/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPBLB
rw
KEYSIZE
rw
CHMOD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GCMPH
rw
DMAOUTEN
rw
DMAINEN
rw
ERRIE
rw
CCFIE
rw
ERRC
rw
CCFC
rw
CHMOD1
rw
MODE
rw
DATATYPE
rw
EN
rw
Toggle Fields.

EN

Bit 0: AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase..

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

DATATYPE

Bits 1-2: Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

Allowed values:
0x0: B_0x0: None
0x1: B_0x1: Half-word (16-bit)
0x2: B_0x2: Byte (8-bit)
0x3: B_0x3: Bit

MODE

Bits 3-4: AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4..

Allowed values:
0x0: B_0x0: Mode 1: encryption
0x1: B_0x1: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
0x2: B_0x2: Mode 3: decryption
0x3: B_0x3: Mode 4: key derivation then single decryption

CHMOD1

Bits 5-6: Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

CCFC

Bit 7: Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: Reading the flag always returns zero..

Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Clear CCF

ERRC

Bit 8: Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: Reading the flag always returns zero..

Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Clear RDERR and WRERR flags

CCFIE

Bit 9: CCF interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set:.

Allowed values:
0x0: B_0x0: Disable (mask)
0x1: B_0x1: Enable

ERRIE

Bit 10: Error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set:.

Allowed values:
0x0: B_0x0: Disable (mask)
0x1: B_0x1: Enable

DMAINEN

Bit 11: DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended..

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

DMAOUTEN

Bit 12: DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended..

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

GCMPH

Bits 13-14: GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield)..

Allowed values:
0x0: B_0x0: Init phase
0x1: B_0x1: Header phase
0x2: B_0x2: Payload phase
0x3: B_0x3: Final phase

CHMOD2

Bit 16: Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

KEYSIZE

Bit 18: Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access..

Allowed values:
0x0: B_0x0: 128
0x1: B_0x1: 256

NPBLB

Bits 20-23: Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ....

Allowed values:
0x0: B_0x0: All bytes are valid (no padding)
0x1: B_0x1: Padding for one least-significant byte of last block
0xF: B_0xF: Padding for 15 least-significant bytes of last block

AES_SR

AES status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
WRERR
r
RDERR
r
CCF
r
Toggle Fields.

CCF

Bit 0: Computation completed flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1..

Allowed values:
0x0: B_0x0: Not completed
0x1: B_0x1: Completed

RDERR

Bit 1: Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected read returns zero..

Allowed values:
0x0: B_0x0: Not detected
0x1: B_0x1: Detected

WRERR

Bit 2: Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected write is ignored..

Allowed values:
0x0: B_0x0: Not detected
0x1: B_0x1: Detected

BUSY

Bit 3: Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process..

Allowed values:
0x0: B_0x0: Idle
0x1: B_0x1: Busy

AES_DINR

AES data input register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
rw
Toggle Fields.

DIN

Bits 0-31: Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the AES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext The data swap operation is described in page 499..

AES_DOUTR

AES data output register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle Fields.

DOUT

Bits 0-31: Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the AES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext The data swap operation is described in page 499..

AES_KEYR0

AES key register 0

Offset: 0x10, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [31:0] This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key. Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key. The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details..

AES_KEYR1

AES key register 1

Offset: 0x14, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

AES_KEYR2

AES key register 2

Offset: 0x18, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

AES_KEYR3

AES key register 3

Offset: 0x1C, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

AES_IVR0

AES initialization vector register 0

Offset: 0x20, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle Fields.

IVI

Bits 0-31: Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled.

AES_IVR1

AES initialization vector register 1

Offset: 0x24, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle Fields.

IVI

Bits 0-31: Initialization vector input, bits [63:32] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield..

AES_IVR2

AES initialization vector register 2

Offset: 0x28, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle Fields.

IVI

Bits 0-31: Initialization vector input, bits [95:64] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield..

AES_IVR3

AES initialization vector register 3

Offset: 0x2C, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle Fields.

IVI

Bits 0-31: Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield..

AES_KEYR4

AES key register 4

Offset: 0x30, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

AES_KEYR5

AES key register 5

Offset: 0x34, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [191:160] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

AES_KEYR6

AES key register 6

Offset: 0x38, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

AES_KEYR7

AES key register 7

Offset: 0x3C, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
rw
Toggle Fields.

KEY

Bits 0-31: Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield..

AES_SUSP0R

AES suspend registers

Offset: 0x40, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

AES_SUSP1R

AES suspend registers

Offset: 0x44, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

AES_SUSP2R

AES suspend registers

Offset: 0x48, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

AES_SUSP3R

AES suspend registers

Offset: 0x4C, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

AES_SUSP4R

AES suspend registers

Offset: 0x50, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

AES_SUSP5R

AES suspend registers

Offset: 0x54, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

AES_SUSP6R

AES suspend registers

Offset: 0x58, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

AES_SUSP7R

AES suspend registers

Offset: 0x5C, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle Fields.

SUSP

Bits 0-31: AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers..

CRC

0x40023000: Cyclic redundancy check calculation unit

3/8 fields covered. Toggle Registers.

CRC_DR

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-31: Data register bits.

CRC_IDR

Independent data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle Fields.

IDR

Bits 0-31: General-purpose 32-bit data register bits.

CRC_CR

Control register

Offset: 0x8, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw
REV_IN
rw
POLYSIZE
rw
RESET
w
Toggle Fields.

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

Allowed values:
0x0: B_0x0: 32 bit polynomial
0x1: B_0x1: 16 bit polynomial
0x2: B_0x2: 8 bit polynomial
0x3: B_0x3: 7 bit polynomial

REV_IN

Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data.

Allowed values:
0x0: B_0x0: Bit order not affected
0x1: B_0x1: Bit reversal done by byte
0x2: B_0x2: Bit reversal done by half-word
0x3: B_0x3: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

Allowed values:
0x0: B_0x0: Bit order not affected
0x1: B_0x1: Bit-reversed output format

CRC_INIT

Initial CRC value

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle Fields.

CRC_INIT

Bits 0-31: Programmable initial CRC value.

CRC_POL

polynomial

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle Fields.

POL

Bits 0-31: Programmable polynomial.

DAC

0x40007400: DAC

28/48 fields covered. Toggle Registers.

DAC_CR

DAC control register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN2
rw
DMAUDRIE2
rw
DMAEN2
rw
MAMP2
rw
WAVE2
rw
TSEL2
rw
TEN2
rw
EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEN1
rw
DMAUDRIE1
rw
DMAEN1
rw
MAMP1
rw
WAVE1
rw
TSEL1
rw
TEN1
rw
EN1
rw
Toggle Fields.

EN1

Bit 0: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1..

Allowed values:
0x0: B_0x0: DAC channel1 disabled
0x1: B_0x1: DAC channel1 enabled

TEN1

Bit 1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle..

Allowed values:
0x0: B_0x0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register
0x1: B_0x1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register

TSEL1

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0x0: B_0x0: SWTRIG1
0x1: B_0x1: dac_ch1_trg1
0x2: B_0x2: dac_ch1_trg2
0xF: B_0xF: dac_ch1_trg15

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0x0: B_0x0: wave generation disabled
0x1: B_0x1: Noise wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

DMAEN1

Bit 12: DAC channel1 DMA enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: DAC channel1 DMA mode disabled
0x1: B_0x1: DAC channel1 DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: DAC channel1 DMA Underrun Interrupt disabled
0x1: B_0x1: DAC channel1 DMA Underrun Interrupt enabled

CEN1

Bit 14: DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

Allowed values:
0x0: B_0x0: DAC channel1 in Normal operating mode
0x1: B_0x1: DAC channel1 in calibration mode

EN2

Bit 16: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. Note: These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 disabled
0x1: B_0x1: DAC channel2 enabled

TEN2

Bit 17: DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_pclk clock cycle later to the DAC_DOR2 register
0x1: B_0x1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_pclk clock cycles later to the DAC_DOR2 register

TSEL2

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: SWTRIG2
0x1: B_0x1: dac_ch2_trg1
0x2: B_0x2: dac_ch2_trg2
0xF: B_0xF: dac_ch2_trg15

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: wave generation disabled
0x1: B_0x1: Noise wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

DMAEN2

Bit 28: DAC channel2 DMA enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 DMA mode disabled
0x1: B_0x1: DAC channel2 DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 DMA underrun interrupt disabled
0x1: B_0x1: DAC channel2 DMA underrun interrupt enabled

CEN2

Bit 30: DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 in Normal operating mode
0x1: B_0x1: DAC channel2 in calibration mode

DAC_SWTRGR

DAC software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w
SWTRIG1
w
Toggle Fields.

SWTRIG1

Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..

Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger

SWTRIG2

Bit 1: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger

DAC_DHR12R1

DAC channel1 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DAC_DHR12L1

DAC channel1 12-bit left aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DAC_DHR8R1

DAC channel1 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1..

DAC_DHR12R2

DAC channel2 12-bit right aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2..

DAC_DHR12L2

DAC channel2 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2..

DAC_DHR8R2

DAC channel2 8-bit right-aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DAC_DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DAC_DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DAC_DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DAC_DOR1

DAC channel1 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle Fields.

DACC1DOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

DAC_DOR2

DAC channel2 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle Fields.

DACC2DOR

Bits 0-11: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2..

DAC_SR

DAC status register

Offset: 0x34, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
r
CAL_FLAG2
r
DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST1
r
CAL_FLAG1
r
DMAUDR1
rw
Toggle Fields.

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel1
0x1: B_0x1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG1

Bit 14: DAC channel1 calibration offset status This bit is set and cleared by hardware.

Allowed values:
0x0: B_0x0: calibration trimming value is lower than the offset correction value
0x1: B_0x1: calibration trimming value is equal or greater than the offset correction value

BWST1

Bit 15: DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization)..

Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel2
0x1: B_0x1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate).

CAL_FLAG2

Bit 30: DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: calibration trimming value is lower than the offset correction value
0x1: B_0x1: calibration trimming value is equal or greater than the offset correction value

BWST2

Bit 31: DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written

DAC_CCR

DAC calibration control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM1
rw
Toggle Fields.

OTRIM1

Bits 0-4: DAC channel1 offset trimming value.

OTRIM2

Bits 16-20: DAC channel2 offset trimming value These bits are available only on dual-channel DACs. Refer to implementation..

DAC_MCR

DAC mode control register

Offset: 0x3C, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE1
rw
Toggle Fields.

MODE1

Bits 0-2: DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample & hold mode Note: This register can be modified only when EN1=0..

Allowed values:
0x0: B_0x0: DAC channel1 is connected to external pin with Buffer enabled
0x1: B_0x1: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x2: B_0x2: DAC channel1 is connected to external pin with Buffer disabled
0x3: B_0x3: DAC channel1 is connected to on chip peripherals with Buffer disabled
0x4: B_0x4: DAC channel1 is connected to external pin with Buffer enabled
0x5: B_0x5: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x6: B_0x6: DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled
0x7: B_0x7: DAC channel1 is connected to on chip peripherals with Buffer disabled

MODE2

Bits 16-18: DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel2 mode: DAC channel2 in Normal mode DAC channel2 in Sample and hold mode Note: This register can be modified only when EN2=0. Refer to for the availability of DAC channel2..

Allowed values:
0x0: B_0x0: DAC channel2 is connected to external pin with Buffer enabled
0x1: B_0x1: DAC channel2 is connected to external pin and to on chip peripherals with buffer enabled
0x2: B_0x2: DAC channel2 is connected to external pin with buffer disabled
0x3: B_0x3: DAC channel2 is connected to on chip peripherals with Buffer disabled
0x4: B_0x4: DAC channel2 is connected to external pin with Buffer enabled
0x5: B_0x5: DAC channel2 is connected to external pin and to on chip peripherals with Buffer enabled
0x6: B_0x6: DAC channel2 is connected to external pin and to on chip peripherals with Buffer disabled
0x7: B_0x7: DAC channel2 is connected to on chip peripherals with Buffer disabled

DAC_SHSR1

DAC Sample and Hold sample time register 1

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE1
rw
Toggle Fields.

TSAMPLE1

Bits 0-9: DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1=1, the write operation is ignored..

DAC_SHSR2

DAC Sample and Hold sample time register 2

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE2
rw
Toggle Fields.

TSAMPLE2

Bits 0-9: DAC channel2 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is low, if BWST2=1, the write operation is ignored..

DAC_SHHR

DAC Sample and Hold hold time register

Offset: 0x48, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD1
rw
Toggle Fields.

THOLD1

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode) Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN1=0..

THOLD2

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode). Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation..

DAC_SHRR

DAC Sample and Hold refresh time register

Offset: 0x4C, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH1
rw
Toggle Fields.

TREFRESH1

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN1=0..

TREFRESH2

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation..

DBG

0x40015800: Debug support

19/19 fields covered. Toggle Registers.

IDCODE

MCU Device ID Code Register

Offset: 0x0, reset: 0x0, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle Fields.

DEV_ID

Bits 0-11: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

DBG_CR

DBG configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_STANDBY
rw
DBG_STOP
rw
Toggle Fields.

DBG_STOP

Bit 1: Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration..

Allowed values:
0x0: B_0x0: All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator.
0x1: B_0x1: FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events.

DBG_STANDBY

Bit 2: Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode..

Allowed values:
0x0: B_0x0: Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby)
0x1: B_0x1: Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset.

DBG_APB_FZ1

DBG APB freeze register 1

Offset: 0x8, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
rw
DBG_LPTIM2_STOP
rw
DBG_I2C1_SMBUS_TIMEOUT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw
DBG_WWDG_STOP
rw
DBG_RTC_STOP
rw
DBG_TIM7_STOP
rw
DBG_TIM6_STOP
rw
DBG_TIM3_STOP
rw
DBG_TIM2_STOP
rw
Toggle Fields.

DBG_TIM2_STOP

Bit 0: Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM3_STOP

Bit 1: Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM6_STOP

Bit 4: Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM7_STOP

Bit 5: Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_RTC_STOP

Bit 10: Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_WWDG_STOP

Bit 11: Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_IWDG_STOP

Bit 12: Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout when core is halted.

Allowed values:
0x0: B_0x0: Same behavior as in normal mode
0x1: B_0x1: The SMBUS timeout is frozen

DBG_LPTIM2_STOP

Bit 30: Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_LPTIM1_STOP

Bit 31: Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_APB_FZ2

DBG APB freeze register 2

Offset: 0xC, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw
DBG_TIM16_STOP
rw
DBG_TIM15_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM14_STOP
rw
DBG_TIM1_STOP
rw
Toggle Fields.

DBG_TIM1_STOP

Bit 11: Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM14_STOP

Bit 15: Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM15_STOP

Bit 16: Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx..

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM16_STOP

Bit 17: Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DBG_TIM17_STOP

Bit 18: Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:.

Allowed values:
0x0: B_0x0: Enable
0x1: B_0x1: Disable

DMA1

1073872896: DMA controller

56/71 fields covered. Toggle Registers.

ISR

low interrupt status register

Offset: 0x0, reset: 0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r
HTIF7
r
TCIF7
r
GIF7
r
TEIF6
r
HTIF6
r
TCIF6
r
GIF6
r
TEIF5
r
HTIF5
r
TCIF5
r
GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r
HTIF4
r
TCIF4
r
GIF4
r
TEIF3
r
HTIF3
r
TCIF3
r
GIF3
r
TEIF2
r
HTIF2
r
TCIF2
r
GIF2
r
TEIF1
r
HTIF1
r
TCIF1
r
GIF1
r
Toggle Fields.

GIF1

Bit 0: Channel 1 global interrupt flag.

TCIF1

Bit 1: Channel 1 transfer complete flag.

HTIF1

Bit 2: Channel 1 half transfer flag.

TEIF1

Bit 3: Channel 1 transfer error flag.

GIF2

Bit 4: Channel 2 global interrupt flag.

TCIF2

Bit 5: Channel 2 transfer complete flag.

HTIF2

Bit 6: Channel 2 half transfer flag.

TEIF2

Bit 7: Channel 2 transfer error flag.

GIF3

Bit 8: Channel 3 global interrupt flag.

TCIF3

Bit 9: Channel 3 transfer complete flag.

HTIF3

Bit 10: Channel 3 half transfer flag.

TEIF3

Bit 11: Channel 3 transfer error flag.

GIF4

Bit 12: Channel 4 global interrupt flag.

TCIF4

Bit 13: Channel 4 transfer complete flag.

HTIF4

Bit 14: Channel 4 half transfer flag.

TEIF4

Bit 15: Channel 4 transfer error flag.

GIF5

Bit 16: Channel 5 global interrupt flag.

TCIF5

Bit 17: Channel 5 transfer complete flag.

HTIF5

Bit 18: Channel 5 half transfer flag.

TEIF5

Bit 19: Channel 5 transfer error flag.

GIF6

Bit 20: Channel 6 global interrupt flag.

TCIF6

Bit 21: Channel 6 transfer complete flag.

HTIF6

Bit 22: Channel 6 half transfer flag.

TEIF6

Bit 23: Channel 6 transfer error flag.

GIF7

Bit 24: Channel 7 global interrupt flag.

TCIF7

Bit 25: Channel 7 transfer complete flag.

HTIF7

Bit 26: Channel 7 half transfer flag.

TEIF7

Bit 27: Channel 7 transfer error flag.

IFCR

high interrupt status register

Offset: 0x4, reset: 0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF7
r
CHTIF7
r
CTCIF7
r
CGIF7
r
CTEIF6
r
CHTIF6
r
CTCIF6
r
CGIF6
r
CTEIF5
r
CHTIF5
r
CTCIF5
r
CGIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF15
r
CHTIF4
r
CTCIF4
r
CGIF4
r
CTEIF3
r
CHTIF3
r
CTCIF3
r
CGIF3
r
CTEIF2
r
CHTIF2
r
CTCIF2
r
CGIF2
r
CTEIF1
r
CHTIF1
r
CTCIF1
r
CGIF1
r
Toggle Fields.

CGIF1

Bit 0: Clear channel 1 global interrupt flag.

CTCIF1

Bit 1: Clear channel 1 transfer complete flag.

CHTIF1

Bit 2: Clear channel 1 half transfer flag.

CTEIF1

Bit 3: Clear channel 1 transfer error flag.

CGIF2

Bit 4: Clear channel 2 global interrupt flag.

CTCIF2

Bit 5: Clear channel 2 transfer complete flag.

CHTIF2

Bit 6: Clear channel 2 half transfer flag.

CTEIF2

Bit 7: Clear channel 2 transfer error flag.

CGIF3

Bit 8: Clear channel 3 global interrupt flag.

CTCIF3

Bit 9: Clear channel 3 transfer complete flag.

CHTIF3

Bit 10: Clear channel 3 half transfer flag.

CTEIF3

Bit 11: Clear channel 3 transfer error flag.

CGIF4

Bit 12: Clear channel 4 global interrupt flag.

CTCIF4

Bit 13: Clear channel 4 transfer complete flag.

CHTIF4

Bit 14: Clear channel 4 half transfer flag.

CTEIF15

Bit 15: Clear channel 4 transfer error flag.

CGIF5

Bit 16: Clear channel 5 global interrupt flag.

CTCIF5

Bit 17: Clear channel 5 transfer complete flag.

CHTIF5

Bit 18: Clear channel 5 half transfer flag.

CTEIF5

Bit 19: Clear channel 5 transfer error flag.

CGIF6

Bit 20: Clear channel 6 global interrupt flag.

CTCIF6

Bit 21: Clear channel 6 transfer complete flag.

CHTIF6

Bit 22: Clear channel 6 half transfer flag.

CTEIF6

Bit 23: Clear channel 6 transfer error flag.

CGIF7

Bit 24: Clear channel 7 global interrupt flag.

CTCIF7

Bit 25: Clear channel 7 transfer complete flag.

CHTIF7

Bit 26: Clear channel 7 half transfer flag.

CTEIF7

Bit 27: Clear channel 7 transfer error flag.

PAR

DMA channel 1 peripheral address

Offset: 0x8, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

MAR

DMA channel 1 memory address

Offset: 0xC, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

DMA2

1073873920: DMA controller

40/55 fields covered. Toggle Registers.

ISR

low interrupt status register

Offset: 0x0, reset: 0, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF5
r
HTIF5
r
TCIF5
r
GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r
HTIF4
r
TCIF4
r
GIF4
r
TEIF3
r
HTIF3
r
TCIF3
r
GIF3
r
TEIF2
r
HTIF2
r
TCIF2
r
GIF2
r
TEIF1
r
HTIF1
r
TCIF1
r
GIF1
r
Toggle Fields.

GIF1

Bit 0: Channel 1 global interrupt flag.

TCIF1

Bit 1: Channel 1 transfer complete flag.

HTIF1

Bit 2: Channel 1 half transfer flag.

TEIF1

Bit 3: Channel 1 transfer error flag.

GIF2

Bit 4: Channel 2 global interrupt flag.

TCIF2

Bit 5: Channel 2 transfer complete flag.

HTIF2

Bit 6: Channel 2 half transfer flag.

TEIF2

Bit 7: Channel 2 transfer error flag.

GIF3

Bit 8: Channel 3 global interrupt flag.

TCIF3

Bit 9: Channel 3 transfer complete flag.

HTIF3

Bit 10: Channel 3 half transfer flag.

TEIF3

Bit 11: Channel 3 transfer error flag.

GIF4

Bit 12: Channel 4 global interrupt flag.

TCIF4

Bit 13: Channel 4 transfer complete flag.

HTIF4

Bit 14: Channel 4 half transfer flag.

TEIF4

Bit 15: Channel 4 transfer error flag.

GIF5

Bit 16: Channel 5 global interrupt flag.

TCIF5

Bit 17: Channel 5 transfer complete flag.

HTIF5

Bit 18: Channel 5 half transfer flag.

TEIF5

Bit 19: Channel 5 transfer error flag.

IFCR

high interrupt status register

Offset: 0x4, reset: 0, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF5
r
CHTIF5
r
CTCIF5
r
CGIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF15
r
CHTIF4
r
CTCIF4
r
CGIF4
r
CTEIF3
r
CHTIF3
r
CTCIF3
r
CGIF3
r
CTEIF2
r
CHTIF2
r
CTCIF2
r
CGIF2
r
CTEIF1
r
CHTIF1
r
CTCIF1
r
CGIF1
r
Toggle Fields.

CGIF1

Bit 0: Clear channel 1 global interrupt flag.

CTCIF1

Bit 1: Clear channel 1 transfer complete flag.

CHTIF1

Bit 2: Clear channel 1 half transfer flag.

CTEIF1

Bit 3: Clear channel 1 transfer error flag.

CGIF2

Bit 4: Clear channel 2 global interrupt flag.

CTCIF2

Bit 5: Clear channel 2 transfer complete flag.

CHTIF2

Bit 6: Clear channel 2 half transfer flag.

CTEIF2

Bit 7: Clear channel 2 transfer error flag.

CGIF3

Bit 8: Clear channel 3 global interrupt flag.

CTCIF3

Bit 9: Clear channel 3 transfer complete flag.

CHTIF3

Bit 10: Clear channel 3 half transfer flag.

CTEIF3

Bit 11: Clear channel 3 transfer error flag.

CGIF4

Bit 12: Clear channel 4 global interrupt flag.

CTCIF4

Bit 13: Clear channel 4 transfer complete flag.

CHTIF4

Bit 14: Clear channel 4 half transfer flag.

CTEIF15

Bit 15: Clear channel 4 transfer error flag.

CGIF5

Bit 16: Clear channel 5 global interrupt flag.

CTCIF5

Bit 17: Clear channel 5 transfer complete flag.

CHTIF5

Bit 18: Clear channel 5 half transfer flag.

CTEIF5

Bit 19: Clear channel 5 transfer error flag.

PAR

DMA channel 1 peripheral address

Offset: 0x8, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

MAR

DMA channel 1 memory address

Offset: 0xC, reset: 0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

DMAMUX

0x40020800: DMAMUX

51/91 fields covered. Toggle Registers.

DMAMUX_C0CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x0, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAMUX_C1CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAMUX_C2CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAMUX_C3CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0xC, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAMUX_C4CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x10, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAMUX_C5CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x14, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAMUX_C6CR

DMAMUX request line multiplexer channel x configuration register

Offset: 0x18, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle Fields.

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt disabled
0x1: B_0x1: interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0x0: B_0x0: event generation disabled
0x1: B_0x1: event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0x0: B_0x0: synchronization disabled
0x1: B_0x1: synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0x0: B_0x0: no event, i.e. no synchronization nor detection.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..

DMAMUX_CSR

DMAMUX request line multiplexer interrupt channel status register

Offset: 0x80, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF6
r
SOF5
r
SOF4
r
SOF3
r
SOF2
r
SOF1
r
SOF0
r
Toggle Fields.

SOF0

Bit 0: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF1

Bit 1: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF2

Bit 2: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF3

Bit 3: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF4

Bit 4: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF5

Bit 5: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF6

Bit 6: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

DMAMUX_CFR

DMAMUX request line multiplexer interrupt clear flag register

Offset: 0x84, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF6
w
CSOF5
w
CSOF4
w
CSOF3
w
CSOF2
w
CSOF1
w
CSOF0
w
Toggle Fields.

CSOF0

Bit 0: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF1

Bit 1: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF2

Bit 2: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF3

Bit 3: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF4

Bit 4: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF5

Bit 5: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF6

Bit 6: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

DMAMUX_RG0CR

DMAMUX request generator channel x configuration register

Offset: 0x100, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt on a trigger overrun event occurrence is disabled
0x1: B_0x1: interrupt on a trigger overrun event occurrence is enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0x0: B_0x0: DMA request generator channel x disabled
0x1: B_0x1: DMA request generator channel x enabled

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

Allowed values:
0x0: B_0x0: no event. I.e. none trigger detection nor generation.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

DMAMUX_RG1CR

DMAMUX request generator channel x configuration register

Offset: 0x104, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt on a trigger overrun event occurrence is disabled
0x1: B_0x1: interrupt on a trigger overrun event occurrence is enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0x0: B_0x0: DMA request generator channel x disabled
0x1: B_0x1: DMA request generator channel x enabled

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

Allowed values:
0x0: B_0x0: no event. I.e. none trigger detection nor generation.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

DMAMUX_RG2CR

DMAMUX request generator channel x configuration register

Offset: 0x108, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt on a trigger overrun event occurrence is disabled
0x1: B_0x1: interrupt on a trigger overrun event occurrence is enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0x0: B_0x0: DMA request generator channel x disabled
0x1: B_0x1: DMA request generator channel x enabled

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

Allowed values:
0x0: B_0x0: no event. I.e. none trigger detection nor generation.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

DMAMUX_RG3CR

DMAMUX request generator channel x configuration register

Offset: 0x10C, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle Fields.

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0x0: B_0x0: interrupt on a trigger overrun event occurrence is disabled
0x1: B_0x1: interrupt on a trigger overrun event occurrence is enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0x0: B_0x0: DMA request generator channel x disabled
0x1: B_0x1: DMA request generator channel x enabled

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

Allowed values:
0x0: B_0x0: no event. I.e. none trigger detection nor generation.
0x1: B_0x1: rising edge
0x2: B_0x2: falling edge
0x3: B_0x3: rising and falling edge

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..

DMAMUX_RGSR

DMAMUX request generator interrupt status register

Offset: 0x140, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF3
r
OF2
r
OF1
r
OF0
r
Toggle Fields.

OF0

Bit 0: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

OF1

Bit 1: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

OF2

Bit 2: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

OF3

Bit 3: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..

DMAMUX_RGCFR

DMAMUX request generator interrupt clear flag register

Offset: 0x144, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF3
w
COF2
w
COF1
w
COF0
w
Toggle Fields.

COF0

Bit 0: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

COF1

Bit 1: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

COF2

Bit 2: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

COF3

Bit 3: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..

GPIOA

0x50000000: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xEBFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x0C000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x24000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw
AFSEL6
rw
AFSEL5
rw
AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw
AFSEL2
rw
AFSEL1
rw
AFSEL0
rw
Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw
AFSEL14
rw
AFSEL13
rw
AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw
AFSEL10
rw
AFSEL9
rw
AFSEL8
rw
Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOB

0x50000400: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw
AFSEL6
rw
AFSEL5
rw
AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw
AFSEL2
rw
AFSEL1
rw
AFSEL0
rw
Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw
AFSEL14
rw
AFSEL13
rw
AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw
AFSEL10
rw
AFSEL9
rw
AFSEL8
rw
Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOC

0x50000800: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw
AFSEL6
rw
AFSEL5
rw
AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw
AFSEL2
rw
AFSEL1
rw
AFSEL0
rw
Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw
AFSEL14
rw
AFSEL13
rw
AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw
AFSEL10
rw
AFSEL9
rw
AFSEL8
rw
Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOD

0x50000C00: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw
AFSEL6
rw
AFSEL5
rw
AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw
AFSEL2
rw
AFSEL1
rw
AFSEL0
rw
Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw
AFSEL14
rw
AFSEL13
rw
AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw
AFSEL10
rw
AFSEL9
rw
AFSEL8
rw
Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOE

0x50001000: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw
AFSEL6
rw
AFSEL5
rw
AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw
AFSEL2
rw
AFSEL1
rw
AFSEL0
rw
Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw
AFSEL14
rw
AFSEL13
rw
AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw
AFSEL10
rw
AFSEL9
rw
AFSEL8
rw
Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOF

0x50001400: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw
AFSEL6
rw
AFSEL5
rw
AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw
AFSEL2
rw
AFSEL1
rw
AFSEL0
rw
Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw
AFSEL14
rw
AFSEL13
rw
AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw
AFSEL10
rw
AFSEL9
rw
AFSEL8
rw
Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

HDMI_CEC

0x40007800: HDMI-CEC

25/40 fields covered. Toggle Registers.

CEC_CR

CEC control register

Offset: 0x0, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEOM
rw
TXSOM
rw
CECEN
rw
Toggle Fields.

CECEN

Bit 0: CEC enable The CECEN bit is set and cleared by software. CECEN = 1 starts message reception and enables the TXSOM control. CECEN = 0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission..

Allowed values:
0x0: B_0x0: CEC peripheral is off.
0x1: B_0x1: CEC peripheral is on.

TXSOM

Bit 1: Tx start of message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission starts after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND = 1), in case of transmission underrun (TXUDR = 1), negative acknowledge (TXACKE = 1), and transmission error (TXERR = 1). It is also cleared by CECEN = 0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST = 1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN = 1. TXSOM must be set when transmission data is available into TXDR. HEADER first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR that is used only for reception..

Allowed values:
0x0: B_0x0: No CEC transmission is on-going
0x1: B_0x1: CEC transmission command

TXEOM

Bit 2: Tx end of message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN = 1. TXEOM must be set before writing transmission data to TXDR. If TXEOM is set when TXSOM = 0, transmitted message consists of 1 byte (HEADER) only (PING message)..

Allowed values:
0x0: B_0x0: TXDR data byte is transmitted with EOM = 0
0x1: B_0x1: TXDR data byte is transmitted with EOM = 1

CEC_CFGR

This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.

Offset: 0x4, reset: 0x00000000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSTN
rw
OAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFTOP
rw
BRDNOGEN
rw
LBPEGEN
rw
BREGEN
rw
BRESTP
rw
RXTOL
rw
SFT
rw
Toggle Fields.

SFT

Bits 0-2: Signal free time SFT bits are set by software. In the SFT = 0x0 configuration, the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. 0x0 2.5 data-bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST = 1, TXERR = 1, TXUDR = 1 or TXACKE = 1) 4 data-bit periods if CEC is the new bus initiator 6 data-bit periods if CEC is the last bus initiator with successful transmission (TXEOM = 1).

Allowed values:
0x1: B_0x1: 0.5 nominal data bit periods
0x2: B_0x2: 1.5 nominal data bit periods
0x3: B_0x3: 2.5 nominal data bit periods
0x4: B_0x4: 3.5 nominal data bit periods
0x5: B_0x5: 4.5 nominal data bit periods
0x6: B_0x6: 5.5 nominal data bit periods
0x7: B_0x7: 6.5 nominal data bit periods

RXTOL

Bit 3: Rx-tolerance The RXTOL bit is set and cleared by software. Start-bit, +/- 200 µs rise, +/- 200 µs fall Data-bit: +/- 200 µs rise. +/- 350 µs fall Start-bit: +/- 400 µs rise, +/- 400 µs fall Data-bit: +/-300 µs rise, +/- 500 µs fall.

Allowed values:
0x0: B_0x0: Standard tolerance margin:
0x1: B_0x1: Extended tolerance

BRESTP

Bit 4: Rx-stop on bit rising error The BRESTP bit is set and cleared by software..

Allowed values:
0x0: B_0x0: BRE detection does not stop reception of the CEC message. Data bit is sampled at 1.05 ms.
0x1: B_0x1: BRE detection stops message reception.

BREGEN

Bit 5: Generate error-bit on bit rising error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon BRE detection with BRESTP = 1 in broadcast even if BREGEN = 0..

Allowed values:
0x0: B_0x0: BRE detection does not generate an error-bit on the CEC line.
0x1: B_0x1: BRE detection generates an error-bit on the CEC line (if BRESTP is set).

LBPEGEN

Bit 6: Generate error-bit on long bit period error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon LBPE detection in broadcast even if LBPEGEN = 0..

Allowed values:
0x0: B_0x0: LBPE detection does not generate an error-bit on the CEC line.
0x1: B_0x1: LBPE detection generates an error-bit on the CEC line.

BRDNOGEN

Bit 7: Avoid error-bit generation in broadcast The BRDNOGEN bit is set and cleared by software. error-bit on the CEC line. LBPE detection with LBPEGEN = 0 on a broadcast message generates an error-bit on the CEC line..

Allowed values:
0x0: B_0x0: BRE detection with BRESTP = 1 and BREGEN = 0 on a broadcast message generates an
0x1: B_0x1: Error-bit is not generated in the same condition as above. An error-bit is not generated even in case of an SBPE detection in a broadcast message if listen mode is set.

SFTOP

Bit 8: SFT option bit The SFTOPT bit is set and cleared by software..

Allowed values:
0x0: B_0x0: SFT timer starts when TXSOM is set by software.
0x1: B_0x1: SFT timer starts automatically at the end of message transmission/reception.

OAR

Bits 16-30: Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN = 1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received..

LSTN

Bit 31: Listen mode LSTN bit is set and cleared by software..

Allowed values:
0x0: B_0x0: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.
0x1: B_0x1: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.

CEC_TXDR

CEC Tx data register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXD
w
Toggle Fields.

TXD

Bits 0-7: Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1.

CEC_RXDR

CEC Rx Data Register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXD
r
Toggle Fields.

RXD

Bits 0-7: Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line..

CEC_ISR

CEC Interrupt and Status Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACKE
rw
TXERR
rw
TXUDR
rw
TXEND
rw
TXBR
rw
ARBLST
rw
RXACKE
rw
LBPE
rw
SBPE
rw
BRE
rw
RXOVR
rw
RXEND
rw
RXBR
rw
Toggle Fields.

RXBR

Bit 0: Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1..

RXEND

Bit 1: End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1..

RXOVR

Bit 2: Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1..

BRE

Bit 3: Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1..

SBPE

Bit 4: Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1..

LBPE

Bit 5: Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1..

RXACKE

Bit 6: Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1..

ARBLST

Bit 7: Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1..

TXBR

Bit 8: Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1..

TXEND

Bit 9: End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1..

TXUDR

Bit 10: Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1.

TXERR

Bit 11: Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1..

TXACKE

Bit 12: Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1..

CEC_IER

CEC interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACKIE
rw
TXERRIE
rw
TXUDRIE
rw
TXENDIE
rw
TXBRIE
rw
ARBLSTIE
rw
RXACKIE
rw
LBPEIE
rw
SBPEIE
rw
BREIE
rw
RXOVRIE
rw
RXENDIE
rw
RXBRIE
rw
Toggle Fields.

RXBRIE

Bit 0: Rx-byte received interrupt enable The RXBRIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: RXBR interrupt disabled
0x1: B_0x1: RXBR interrupt enabled

RXENDIE

Bit 1: End of reception interrupt enable The RXENDIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: RXEND interrupt disabled
0x1: B_0x1: RXEND interrupt enabled

RXOVRIE

Bit 2: Rx-buffer overrun interrupt enable The RXOVRIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: RXOVR interrupt disabled
0x1: B_0x1: RXOVR interrupt enabled

BREIE

Bit 3: Bit rising error interrupt enable The BREIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: BRE interrupt disabled
0x1: B_0x1: BRE interrupt enabled

SBPEIE

Bit 4: Short bit period error interrupt enable The SBPEIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: SBPE interrupt disabled
0x1: B_0x1: SBPE interrupt enabled

LBPEIE

Bit 5: Long bit period error interrupt enable The LBPEIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: LBPE interrupt disabled
0x1: B_0x1: LBPE interrupt enabled

RXACKIE

Bit 6: Rx-missing acknowledge error interrupt enable The RXACKIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: RXACKE interrupt disabled
0x1: B_0x1: RXACKE interrupt enabled

ARBLSTIE

Bit 7: Arbitration lost interrupt enable The ARBLSTIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: ARBLST interrupt disabled
0x1: B_0x1: ARBLST interrupt enabled

TXBRIE

Bit 8: Tx-byte request interrupt enable The TXBRIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: TXBR interrupt disabled
0x1: B_0x1: TXBR interrupt enabled

TXENDIE

Bit 9: Tx-end of message interrupt enable The TXENDIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: TXEND interrupt disabled
0x1: B_0x1: TXEND interrupt enabled

TXUDRIE

Bit 10: Tx-underrun interrupt enable The TXUDRIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: TXUDR interrupt disabled
0x1: B_0x1: TXUDR interrupt enabled

TXERRIE

Bit 11: Tx-error interrupt enable The TXERRIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: TXERR interrupt disabled
0x1: B_0x1: TXERR interrupt enabled

TXACKIE

Bit 12: Tx-missing acknowledge error interrupt enable The TXACKEIE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: TXACKE interrupt disabled
0x1: B_0x1: TXACKE interrupt enabled

I2C1

0x40005400: Inter-integrated circuit

53/76 fields covered. Toggle Registers.

I2C_CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0x0: B_0x0: Peripheral disable
0x1: B_0x1: Peripheral enable

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0x0: B_0x0: Transmit (TXIS) interrupt disabled
0x1: B_0x1: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0x0: B_0x0: Receive (RXNE) interrupt disabled
0x1: B_0x1: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0x0: B_0x0: Address match (ADDR) interrupts disabled
0x1: B_0x1: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0x0: B_0x0: Not acknowledge (NACKF) received interrupts disabled
0x1: B_0x1: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: Stop detection Interrupt enable.

Allowed values:
0x0: B_0x0: Stop detection (STOPF) interrupt disabled
0x1: B_0x1: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0x0: B_0x0: Transfer Complete interrupt disabled
0x1: B_0x1: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0x0: B_0x0: Error detection interrupts disabled
0x1: B_0x1: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0x0: B_0x0: Digital filter disabled
0x1: B_0x1: Digital filter enabled and filtering capability up to 1 tI2CCLK
0xF: B_0xF: digital filter enabled and filtering capability up to15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0x0: B_0x0: Analog noise filter enabled
0x1: B_0x1: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0x0: B_0x0: DMA mode disabled for transmission
0x1: B_0x1: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0x0: B_0x0: DMA mode disabled for reception
0x1: B_0x1: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0x0: B_0x0: Slave byte control disabled
0x1: B_0x1: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0x0: B_0x0: Clock stretching enabled
0x1: B_0x1: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’.

Allowed values:
0x0: B_0x0: Wakeup from Stop mode disable.
0x1: B_0x1: Wakeup from Stop mode enable.

GCEN

Bit 19: General call enable.

Allowed values:
0x0: B_0x0: General call disabled. Address 0b00000000 is NACKed.
0x1: B_0x1: General call enabled. Address 0b00000000 is ACKed.

SMBHEN

Bit 20: SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: Host Address disabled. Address 0b0001000x is NACKed.
0x1: B_0x1: Host Address enabled. Address 0b0001000x is ACKed.

SMBDEN

Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: Device Default Address disabled. Address 0b1100001x is NACKed.
0x1: B_0x1: Device Default Address enabled. Address 0b1100001x is ACKed.

ALERTEN

Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK).
0x1: B_0x1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK).

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: PEC calculation disabled
0x1: B_0x1: PEC calculation enabled

I2C_CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

9/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0x0: B_0x0: Master requests a write transfer.
0x1: B_0x1: Master requests a read transfer.

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0x0: B_0x0: The master operates in 7-bit addressing mode,
0x1: B_0x1: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0x0: B_0x0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
0x1: B_0x1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0x0: B_0x0: No Start generation.
0x1: B_0x1: Restart/Start generation:

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect..

Allowed values:
0x0: B_0x0: No Stop generation.
0x1: B_0x1: Stop generation after current byte transfer.

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0x0: B_0x0: an ACK is sent after current received byte.
0x1: B_0x1: a NACK is sent after current received byte.

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
0x1: B_0x1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0x0: B_0x0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
0x1: B_0x1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: No PEC transfer.
0x1: B_0x1: PEC transmission/reception is requested

I2C_OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0x0: B_0x0: Own address 1 is a 7-bit address.
0x1: B_0x1: Own address 1 is a 10-bit address.

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0x0: B_0x0: Own address 1 disabled. The received slave address OA1 is NACKed.
0x1: B_0x1: Own address 1 enabled. The received slave address OA1 is ACKed.

I2C_OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0x0: B_0x0: No mask
0x1: B_0x1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared.
0x2: B_0x2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared.
0x3: B_0x3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared.
0x4: B_0x4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared.
0x5: B_0x5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared.
0x6: B_0x6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
0x7: B_0x7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0x0: B_0x0: Own address 2 disabled. The received slave address OA2 is NACKed.
0x1: B_0x1: Own address 2 enabled. The received slave address OA2 is ACKed.

I2C_TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

I2C_TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0x0: B_0x0: TIMEOUTA is used to detect SCL low timeout
0x1: B_0x1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0x0: B_0x0: SCL timeout detection is disabled
0x1: B_0x1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1).

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0x0: B_0x0: Extended clock timeout detection is disabled
0x1: B_0x1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1).

I2C_ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0x0: B_0x0: Write transfer, slave enters receiver mode.
0x1: B_0x1: Read transfer, slave enters transmitter mode.

ADDCODE

Bits 17-23: Address match code (Slave mode).

I2C_ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w
TIMOUTCF
w
PECCF
w
OVRCF
w
ARLOCF
w
BERRCF
w
STOPCF
w
NACKCF
w
ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

I2C_PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

I2C_RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

I2C_TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

I2C2

0x40005800: Inter-integrated circuit

53/76 fields covered. Toggle Registers.

I2C_CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0x0: B_0x0: Peripheral disable
0x1: B_0x1: Peripheral enable

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0x0: B_0x0: Transmit (TXIS) interrupt disabled
0x1: B_0x1: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0x0: B_0x0: Receive (RXNE) interrupt disabled
0x1: B_0x1: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0x0: B_0x0: Address match (ADDR) interrupts disabled
0x1: B_0x1: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0x0: B_0x0: Not acknowledge (NACKF) received interrupts disabled
0x1: B_0x1: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: Stop detection Interrupt enable.

Allowed values:
0x0: B_0x0: Stop detection (STOPF) interrupt disabled
0x1: B_0x1: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0x0: B_0x0: Transfer Complete interrupt disabled
0x1: B_0x1: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0x0: B_0x0: Error detection interrupts disabled
0x1: B_0x1: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0x0: B_0x0: Digital filter disabled
0x1: B_0x1: Digital filter enabled and filtering capability up to 1 tI2CCLK
0xF: B_0xF: digital filter enabled and filtering capability up to15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0x0: B_0x0: Analog noise filter enabled
0x1: B_0x1: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0x0: B_0x0: DMA mode disabled for transmission
0x1: B_0x1: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0x0: B_0x0: DMA mode disabled for reception
0x1: B_0x1: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0x0: B_0x0: Slave byte control disabled
0x1: B_0x1: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0x0: B_0x0: Clock stretching enabled
0x1: B_0x1: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’.

Allowed values:
0x0: B_0x0: Wakeup from Stop mode disable.
0x1: B_0x1: Wakeup from Stop mode enable.

GCEN

Bit 19: General call enable.

Allowed values:
0x0: B_0x0: General call disabled. Address 0b00000000 is NACKed.
0x1: B_0x1: General call enabled. Address 0b00000000 is ACKed.

SMBHEN

Bit 20: SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: Host Address disabled. Address 0b0001000x is NACKed.
0x1: B_0x1: Host Address enabled. Address 0b0001000x is ACKed.

SMBDEN

Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: Device Default Address disabled. Address 0b1100001x is NACKed.
0x1: B_0x1: Device Default Address enabled. Address 0b1100001x is ACKed.

ALERTEN

Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK).
0x1: B_0x1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK).

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: PEC calculation disabled
0x1: B_0x1: PEC calculation enabled

I2C_CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

9/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0x0: B_0x0: Master requests a write transfer.
0x1: B_0x1: Master requests a read transfer.

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0x0: B_0x0: The master operates in 7-bit addressing mode,
0x1: B_0x1: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0x0: B_0x0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
0x1: B_0x1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0x0: B_0x0: No Start generation.
0x1: B_0x1: Restart/Start generation:

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect..

Allowed values:
0x0: B_0x0: No Stop generation.
0x1: B_0x1: Stop generation after current byte transfer.

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0x0: B_0x0: an ACK is sent after current received byte.
0x1: B_0x1: a NACK is sent after current received byte.

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
0x1: B_0x1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0x0: B_0x0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
0x1: B_0x1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to ..

Allowed values:
0x0: B_0x0: No PEC transfer.
0x1: B_0x1: PEC transmission/reception is requested

I2C_OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0x0: B_0x0: Own address 1 is a 7-bit address.
0x1: B_0x1: Own address 1 is a 10-bit address.

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0x0: B_0x0: Own address 1 disabled. The received slave address OA1 is NACKed.
0x1: B_0x1: Own address 1 enabled. The received slave address OA1 is ACKed.

I2C_OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0x0: B_0x0: No mask
0x1: B_0x1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared.
0x2: B_0x2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared.
0x3: B_0x3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared.
0x4: B_0x4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared.
0x5: B_0x5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared.
0x6: B_0x6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
0x7: B_0x7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0x0: B_0x0: Own address 2 disabled. The received slave address OA2 is NACKed.
0x1: B_0x1: Own address 2 enabled. The received slave address OA2 is ACKed.

I2C_TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

I2C_TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0x0: B_0x0: TIMEOUTA is used to detect SCL low timeout
0x1: B_0x1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0x0: B_0x0: SCL timeout detection is disabled
0x1: B_0x1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1).

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0x0: B_0x0: Extended clock timeout detection is disabled
0x1: B_0x1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1).

I2C_ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0x0: B_0x0: Write transfer, slave enters receiver mode.
0x1: B_0x1: Read transfer, slave enters transmitter mode.

ADDCODE

Bits 17-23: Address match code (Slave mode).

I2C_ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w
TIMOUTCF
w
PECCF
w
OVRCF
w
ARLOCF
w
BERRCF
w
STOPCF
w
NACKCF
w
ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

I2C_PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

I2C_RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

I2C_TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

IWDG

0x40003000: Independent watchdog

4/7 fields covered. Toggle Registers.

IWDG_KR

Key register

Offset: 0x0, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-15: Key value (write only, read 0x0000).

IWDG_PR

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle Fields.

PR

Bits 0-2: Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset..

Allowed values:
0x0: B_0x0: divider /4
0x1: B_0x1: divider /8
0x2: B_0x2: divider /16
0x3: B_0x3: divider /32
0x4: B_0x4: divider /64
0x5: B_0x5: divider /128
0x6: B_0x6: divider /256
0x7: B_0x7: divider /256

IWDG_RLR

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle Fields.

RL

Bits 0-11: Watchdog counter reload value.

IWDG_SR

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r
RVU
r
PVU
r
Toggle Fields.

PVU

Bit 0: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset..

RVU

Bit 1: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset..

WVU

Bit 2: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset..

IWDG_WINR

Window register

Offset: 0x10, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle Fields.

WIN

Bits 0-11: Watchdog counter window value.

LPTIM1

0x40007C00: Low power timer

31/44 fields covered. Toggle Registers.

LPTIM_ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle Fields.

CMPM

Bit 0: Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value..

ARRM

Bit 1: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register..

EXTTRIG

Bit 2: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register..

CMPOK

Bit 3: Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed..

ARROK

Bit 4: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register..

UP

Bit 5: Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

DOWN

Bit 6: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

LPTIM_ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w
UPCF
w
ARROKCF
w
CMPOKCF
w
EXTTRIGCF
w
ARRMCF
w
CMPMCF
w
Toggle Fields.

CMPMCF

Bit 0: Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register.

ARRMCF

Bit 1: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.

EXTTRIGCF

Bit 2: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.

CMPOKCF

Bit 3: Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register.

ARROKCF

Bit 4: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.

UPCF

Bit 5: Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

DOWNCF

Bit 6: Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

LPTIM_IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0x0: B_0x0: CMPM interrupt disabled
0x1: B_0x1: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0x0: B_0x0: ARRM interrupt disabled
0x1: B_0x1: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0x0: B_0x0: EXTTRIG interrupt disabled
0x1: B_0x1: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0x0: B_0x0: CMPOK interrupt disabled
0x1: B_0x1: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0x0: B_0x0: ARROK interrupt disabled
0x1: B_0x1: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

Allowed values:
0x0: B_0x0: UP interrupt disabled
0x1: B_0x1: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

Allowed values:
0x0: B_0x0: DOWN interrupt disabled
0x1: B_0x1: DOWN interrupt enabled

LPTIM_CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle Fields.

CKSEL

Bit 0: Clock selector The CKSEL bit selects which clock source the LPTIM will use:.

Allowed values:
0x0: B_0x0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
0x1: B_0x1: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes..

Allowed values:
0x0: B_0x0: the rising edge is the active edge used for counting.
0x1: B_0x1: the falling edge is the active edge used for counting
0x2: B_0x2: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
0x3: B_0x3: not allowed

CKFLT

Bits 3-4: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.

Allowed values:
0x0: B_0x0: any external clock signal level change is considered as a valid transition
0x1: B_0x1: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition.
0x2: B_0x2: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition.
0x3: B_0x3: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition.

TRGFLT

Bits 6-7: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.

Allowed values:
0x0: B_0x0: any trigger active level change is considered as a valid trigger
0x1: B_0x1: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger.
0x2: B_0x2: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.
0x3: B_0x3: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger.

PRESC

Bits 9-11: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.

Allowed values:
0x0: B_0x0: /1
0x1: B_0x1: /2
0x2: B_0x2: /4
0x3: B_0x3: /8
0x4: B_0x4: /16
0x5: B_0x5: /32
0x6: B_0x6: /64
0x7: B_0x7: /128

TRIGSEL

Bits 13-15: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details..

Allowed values:
0x0: B_0x0: lptim_ext_trig0
0x1: B_0x1: lptim_ext_trig1
0x2: B_0x2: lptim_ext_trig2
0x3: B_0x3: lptim_ext_trig3
0x4: B_0x4: lptim_ext_trig4
0x5: B_0x5: lptim_ext_trig5
0x6: B_0x6: lptim_ext_trig6
0x7: B_0x7: lptim_ext_trig7

TRIGEN

Bits 17-18: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.

Allowed values:
0x0: B_0x0: software trigger (counting start is initiated by software)
0x1: B_0x1: rising edge is the active edge
0x2: B_0x2: falling edge is the active edge
0x3: B_0x3: both edges are active edges

TIMOUT

Bit 19: Timeout enable The TIMOUT bit controls the Timeout feature.

Allowed values:
0x0: B_0x0: A trigger event arriving when the timer is already started will be ignored
0x1: B_0x1: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: Waveform shape The WAVE bit controls the output shape.

Allowed values:
0x0: B_0x0: Deactivate Set-once mode, PWM or One Pulse waveform depending on how the timer was started, CNTSTRT for PWM or SNGSTRT for One Pulse waveform.
0x1: B_0x1: Activate the Set-once mode

WAVPOL

Bit 21: Waveform shape polarity The WAVEPOL bit controls the output polarity.

Allowed values:
0x0: B_0x0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP registers
0x1: B_0x1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers

PRELOAD

Bit 22: Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality.

Allowed values:
0x0: B_0x0: Registers are updated after each APB bus write access
0x1: B_0x1: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.

Allowed values:
0x0: B_0x0: the counter is incremented following each internal clock pulse
0x1: B_0x1: the counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

Allowed values:
0x0: B_0x0: Encoder mode disabled
0x1: B_0x1: Encoder mode enabled

LPTIM_CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw
COUNTRST
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: LPTIM enable The ENABLE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: LPTIM is disabled
0x1: B_0x1: LPTIM is enabled

SNGSTRT

Bit 1: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware..

CNTSTRT

Bit 2: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware..

COUNTRST

Bit 3: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'..

RSTARE

Bit 4: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content..

LPTIM_CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle Fields.

CMP

Bits 0-15: Compare value.

LPTIM_ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto reload value.

LPTIM_CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-15: Counter value.

LPTIM_CFGR2

LPTIM configuration register 2

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw
IN1SEL
rw
Toggle Fields.

IN1SEL

Bits 0-1: LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to ..

Allowed values:
0x0: B_0x0: lptim_in1_mux0
0x1: B_0x1: lptim_in1_mux1
0x2: B_0x2: lptim_in1_mux2
0x3: B_0x3: lptim_in1_mux3

IN2SEL

Bits 4-5: LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to ..

Allowed values:
0x0: B_0x0: lptim_in2_mux0
0x1: B_0x1: lptim_in2_mux1
0x2: B_0x2: lptim_in2_mux2
0x3: B_0x3: lptim_in2_mux3

LPTIM2

0x40009400: Low power timer

31/44 fields covered. Toggle Registers.

LPTIM_ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle Fields.

CMPM

Bit 0: Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value..

ARRM

Bit 1: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register..

EXTTRIG

Bit 2: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register..

CMPOK

Bit 3: Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed..

ARROK

Bit 4: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register..

UP

Bit 5: Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

DOWN

Bit 6: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

LPTIM_ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w
UPCF
w
ARROKCF
w
CMPOKCF
w
EXTTRIGCF
w
ARRMCF
w
CMPMCF
w
Toggle Fields.

CMPMCF

Bit 0: Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register.

ARRMCF

Bit 1: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.

EXTTRIGCF

Bit 2: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.

CMPOKCF

Bit 3: Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register.

ARROKCF

Bit 4: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.

UPCF

Bit 5: Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

DOWNCF

Bit 6: Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

LPTIM_IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0x0: B_0x0: CMPM interrupt disabled
0x1: B_0x1: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0x0: B_0x0: ARRM interrupt disabled
0x1: B_0x1: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0x0: B_0x0: EXTTRIG interrupt disabled
0x1: B_0x1: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0x0: B_0x0: CMPOK interrupt disabled
0x1: B_0x1: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0x0: B_0x0: ARROK interrupt disabled
0x1: B_0x1: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

Allowed values:
0x0: B_0x0: UP interrupt disabled
0x1: B_0x1: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

Allowed values:
0x0: B_0x0: DOWN interrupt disabled
0x1: B_0x1: DOWN interrupt enabled

LPTIM_CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle Fields.

CKSEL

Bit 0: Clock selector The CKSEL bit selects which clock source the LPTIM will use:.

Allowed values:
0x0: B_0x0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
0x1: B_0x1: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes..

Allowed values:
0x0: B_0x0: the rising edge is the active edge used for counting.
0x1: B_0x1: the falling edge is the active edge used for counting
0x2: B_0x2: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
0x3: B_0x3: not allowed

CKFLT

Bits 3-4: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.

Allowed values:
0x0: B_0x0: any external clock signal level change is considered as a valid transition
0x1: B_0x1: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition.
0x2: B_0x2: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition.
0x3: B_0x3: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition.

TRGFLT

Bits 6-7: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.

Allowed values:
0x0: B_0x0: any trigger active level change is considered as a valid trigger
0x1: B_0x1: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger.
0x2: B_0x2: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.
0x3: B_0x3: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger.

PRESC

Bits 9-11: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.

Allowed values:
0x0: B_0x0: /1
0x1: B_0x1: /2
0x2: B_0x2: /4
0x3: B_0x3: /8
0x4: B_0x4: /16
0x5: B_0x5: /32
0x6: B_0x6: /64
0x7: B_0x7: /128

TRIGSEL

Bits 13-15: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details..

Allowed values:
0x0: B_0x0: lptim_ext_trig0
0x1: B_0x1: lptim_ext_trig1
0x2: B_0x2: lptim_ext_trig2
0x3: B_0x3: lptim_ext_trig3
0x4: B_0x4: lptim_ext_trig4
0x5: B_0x5: lptim_ext_trig5
0x6: B_0x6: lptim_ext_trig6
0x7: B_0x7: lptim_ext_trig7

TRIGEN

Bits 17-18: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.

Allowed values:
0x0: B_0x0: software trigger (counting start is initiated by software)
0x1: B_0x1: rising edge is the active edge
0x2: B_0x2: falling edge is the active edge
0x3: B_0x3: both edges are active edges

TIMOUT

Bit 19: Timeout enable The TIMOUT bit controls the Timeout feature.

Allowed values:
0x0: B_0x0: A trigger event arriving when the timer is already started will be ignored
0x1: B_0x1: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: Waveform shape The WAVE bit controls the output shape.

Allowed values:
0x0: B_0x0: Deactivate Set-once mode, PWM or One Pulse waveform depending on how the timer was started, CNTSTRT for PWM or SNGSTRT for One Pulse waveform.
0x1: B_0x1: Activate the Set-once mode

WAVPOL

Bit 21: Waveform shape polarity The WAVEPOL bit controls the output polarity.

Allowed values:
0x0: B_0x0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP registers
0x1: B_0x1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers

PRELOAD

Bit 22: Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality.

Allowed values:
0x0: B_0x0: Registers are updated after each APB bus write access
0x1: B_0x1: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.

Allowed values:
0x0: B_0x0: the counter is incremented following each internal clock pulse
0x1: B_0x1: the counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..

Allowed values:
0x0: B_0x0: Encoder mode disabled
0x1: B_0x1: Encoder mode enabled

LPTIM_CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw
COUNTRST
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: LPTIM enable The ENABLE bit is set and cleared by software..

Allowed values:
0x0: B_0x0: LPTIM is disabled
0x1: B_0x1: LPTIM is enabled

SNGSTRT

Bit 1: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware..

CNTSTRT

Bit 2: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware..

COUNTRST

Bit 3: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'..

RSTARE

Bit 4: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content..

LPTIM_CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle Fields.

CMP

Bits 0-15: Compare value.

LPTIM_ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto reload value.

LPTIM_CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-15: Counter value.

LPTIM_CFGR2

LPTIM configuration register 2

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw
IN1SEL
rw
Toggle Fields.

IN1SEL

Bits 0-1: LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to ..

Allowed values:
0x0: B_0x0: lptim_in1_mux0
0x1: B_0x1: lptim_in1_mux1
0x2: B_0x2: lptim_in1_mux2
0x3: B_0x3: lptim_in1_mux3

IN2SEL

Bits 4-5: LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to ..

Allowed values:
0x0: B_0x0: lptim_in2_mux0
0x1: B_0x1: lptim_in2_mux1
0x2: B_0x2: lptim_in2_mux2
0x3: B_0x3: lptim_in2_mux3

RNG

0x40025000: Random number generator

9/9 fields covered. Toggle Registers.

RNG_CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CED
rw
IE
rw
RNGEN
rw
Toggle Fields.

RNGEN

Bit 2: True random number generator enable.

Allowed values:
0x0: B_0x0: True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated.
0x1: B_0x1: True random number generator is enabled.

IE

Bit 3: Interrupt Enable.

Allowed values:
0x0: B_0x0: RNG Interrupt is disabled
0x1: B_0x1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY='1', SEIS='1' or CEIS=1 in the RNG_SR register.

CED

Bit 5: Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled..

Allowed values:
0x0: B_0x0: Clock error detection is enable
0x1: B_0x1: Clock error detection is disable

RNG_SR

status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw
CEIS
rw
SECS
r
CECS
r
DRDY
r
Toggle Fields.

DRDY

Bit 0: Data Ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN=0 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY=1..

Allowed values:
0x0: B_0x0: The RNG_DR register is not yet valid, no random data is available.
0x1: B_0x1: The RNG_DR register contains valid random data.

CECS

Bit 1: Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0..

Allowed values:
0x0: B_0x0: The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
0x1: B_0x1: The RNG clock is too slow (fRNGCLK< fHCLK/32).

SECS

Bit 2: Seed error current status One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bit patterns (“01” or “10”) Both noise sources have delivered more than 32 consecutive bits at a constant value (“0” or “1”), or more than 16 consecutive occurrence of two bit patterns (“01” or “10”).

Allowed values:
0x0: B_0x0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.
0x1: B_0x1: At least one of the following faulty sequence has been detected:

CEIS

Bit 5: Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register..

Allowed values:
0x0: B_0x0: The RNG clock is correct (fRNGCLK> fHCLK/32)
0x1: B_0x1: The RNG has been detected too slow (fRNGCLK< fHCLK/32)

SEIS

Bit 6: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register..

Allowed values:
0x0: B_0x0: No faulty sequence detected
0x1: B_0x1: At least one faulty sequence has been detected. See SECS bit description for details.

RNG_DR

data register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle Fields.

RNDATA

Bits 0-31: Random data.

TIM1

0x40012C00: Advanced-timers

106/190 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

OPM

Bit 3: One pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the bit CEN)

DIR

Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

Allowed values:
0x0: B_0x0: Counter used as upcounter
0x1: B_0x1: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed.

Allowed values:
0x0: B_0x0: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1: B_0x1: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2: B_0x2: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3: B_0x3: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT..

Allowed values:
0x0: B_0x0: tDTS=tCK_INT
0x1: B_0x1: tDTS=2*tCK_INT
0x2: B_0x2: tDTS=4*tCK_INT
0x3: B_0x3: Reserved, do not program this value

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

8/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw
OIS6
rw
OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw
OIS3N
rw
OIS3
rw
OIS2N
rw
OIS2
rw
OIS1N
rw
OIS1
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0x0: B_0x0: CCx DMA request sent when CCx event occurs
0x1: B_0x1: CCx DMA requests sent when update event occurs

MMS

Bits 4-6: Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO)

TI1S

Bit 7: TI1 selection.

Allowed values:
0x0: B_0x0: The TIMx_CH1 pin is connected to TI1 input
0x1: B_0x1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: OC1N=0 after a dead-time when MOE=0
0x1: B_0x1: OC1N=1 after a dead-time when MOE=0

OIS2

Bit 10: Output Idle state 2 (OC2 output) Refer to OIS1 bit.

OIS2N

Bit 11: Output Idle state 2 (OC2N output) Refer to OIS1N bit.

OIS3

Bit 12: Output Idle state 3 (OC3 output) Refer to OIS1 bit.

OIS3N

Bit 13: Output Idle state 3 (OC3N output) Refer to OIS1N bit.

OIS4

Bit 14: Output Idle state 4 (OC4 output) Refer to OIS1 bit.

OIS5

Bit 16: Output Idle state 5 (OC5 output) Refer to OIS1 bit.

OIS6

Bit 18: Output Idle state 6 (OC6 output) Refer to OIS1 bit.

MMS2

Bits 20-23: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2: B_0x2: Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2).
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO2)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO2)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO2)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO2)
0x8: B_0x8: Compare - OC5REFC signal is used as trigger output (TRGO2)
0x9: B_0x9: Compare - OC6REFC signal is used as trigger output (TRGO2)
0xA: B_0xA: Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2
0xB: B_0xB: Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2
0xC: B_0xC: Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2
0xD: B_0xD: Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2
0xE: B_0xE: Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2
0xF: B_0xF: Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2

SMCR

slave mode control register

Offset: 0x8, reset: 0x00000000, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS1
rw
OCCS
rw
SMS1
rw
Toggle Fields.

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

OCCS

Bit 3: OCREF clear selection This bit is used to select the OCREF clear source..

Allowed values:
0x0: B_0x0: OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIM1_OR1.OCREF_CLR
0x1: B_0x1: OCREF_CLR_INT is connected to ETRF

TS1

Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/slave mode.

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..

Allowed values:
0x0: B_0x0: Prescaler OFF
0x1: B_0x1: ETRP frequency divided by 2
0x2: B_0x2: ETRP frequency divided by 4
0x3: B_0x3: ETRP frequency divided by 8

ECE

Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

Allowed values:
0x0: B_0x0: External clock mode 2 disabled
0x1: B_0x1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.

Allowed values:
0x0: B_0x0: ETR is non-inverted, active at high level or rising edge.
0x1: B_0x1: ETR is inverted, active at low level or falling edge.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled
0x1: B_0x1: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled
0x1: B_0x1: CC1 interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0x0: B_0x0: CC2 interrupt disabled
0x1: B_0x1: CC2 interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0x0: B_0x0: CC3 interrupt disabled
0x1: B_0x1: CC3 interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0x0: B_0x0: CC4 interrupt disabled
0x1: B_0x1: CC4 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0x0: B_0x0: COM interrupt disabled
0x1: B_0x1: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0x0: B_0x0: Trigger interrupt disabled
0x1: B_0x1: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0x0: B_0x0: Break interrupt disabled
0x1: B_0x1: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled
0x1: B_0x1: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0x0: B_0x0: CC1 DMA request disabled
0x1: B_0x1: CC1 DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0x0: B_0x0: CC2 DMA request disabled
0x1: B_0x1: CC2 DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0x0: B_0x0: CC3 DMA request disabled
0x1: B_0x1: CC3 DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0x0: B_0x0: CC4 DMA request disabled
0x1: B_0x1: CC4 DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0x0: B_0x0: COM DMA request disabled
0x1: B_0x1: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0x0: B_0x0: Trigger DMA request disabled
0x1: B_0x1: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

8/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw
CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
B2IF
rw
BIF
rw
TIF
rw
COMIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag Refer to CC1IF description.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag Refer to CC1IF description.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag Refer to CC1IF description.

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software..

Allowed values:
0x0: B_0x0: No COM event occurred.
0x1: B_0x1: COM interrupt pending.

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

Allowed values:
0x0: B_0x0: No trigger event occurred.
0x1: B_0x1: Trigger interrupt pending.

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

Allowed values:
0x0: B_0x0: No break event occurred.
0x1: B_0x1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register.

B2IF

Bit 8: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active..

Allowed values:
0x0: B_0x0: No break event occurred.
0x1: B_0x1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

CC2OF

Bit 10: Capture/Compare 2 overcapture flag Refer to CC1OF description.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag Refer to CC1OF description.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag Refer to CC1OF description.

SBIF

Bit 13: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation..

Allowed values:
0x0: B_0x0: No break event occurred.
0x1: B_0x1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register.

CC5IF

Bit 16: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output).

CC6IF

Bit 17: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output).

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w
BG
w
TG
w
COMG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:

CC2G

Bit 2: Capture/Compare 2 generation Refer to CC1G description.

CC3G

Bit 3: Capture/Compare 3 generation Refer to CC1G description.

CC4G

Bit 4: Capture/Compare 4 generation Refer to CC1G description.

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated.

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.

B2G

Bit 8: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC2 channel is configured as output
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC2PSC

Bits 10-11: Input capture 2 prescaler Refer to IC1PSC[1:0] description..

IC2F

Bits 12-15: Input capture 2 filter Refer to IC1F[3:0] description..

CCMR2_Input

capture/compare mode register 2 (output mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC3PSC

Bits 2-3: Input capture 3 prescaler Refer to IC1PSC[1:0] description..

IC3F

Bits 4-7: Input capture 3 filter Refer to IC1F[3:0] description..

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC4PSC

Bits 10-11: Input capture 4 prescaler Refer to IC1PSC[1:0] description..

IC4F

Bits 12-15: Input capture 4 filter Refer to IC1F[3:0] description..

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

4/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw
CC6E
rw
CC5P
rw
CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3NE
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2NE
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NE

Bit 2: Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1N active high.
0x1: B_0x1: OC1N active low.

CC2E

Bit 4: Capture/Compare 2 output enable Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output polarity Refer to CC1P description.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable Refer to CC1NE description.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity Refer to CC1NP description.

CC3E

Bit 8: Capture/Compare 3 output enable Refer to CC1E description.

CC3P

Bit 9: Capture/Compare 3 output polarity Refer to CC1P description.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable Refer to CC1NE description.

CC3NP

Bit 11: Capture/Compare 3 complementary output polarity Refer to CC1NP description.

CC4E

Bit 12: Capture/Compare 4 output enable Refer to CC1E description.

CC4P

Bit 13: Capture/Compare 4 output polarity Refer to CC1P description.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity Refer to CC1NP description.

CC5E

Bit 16: Capture/Compare 5 output enable Refer to CC1E description.

CC5P

Bit 17: Capture/Compare 5 output polarity Refer to CC1P description.

CC6E

Bit 20: Capture/Compare 6 output enable Refer to CC1E description.

CC6P

Bit 21: Capture/Compare 6 output polarity Refer to CC1P description.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Counter value.

UIFCPY

Bit 31: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0..

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”)..

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-15: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields.

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle Fields.

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle Fields.

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw
BKBID
rw
BK2DSRM
rw
BKDSRM
rw
BK2P
rw
BK2E
rw
BK2F
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tDTG with tDTG=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtDTG with tDTG=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtDTG with tDTG=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtDTG with tDTG=16xtDTS. Example if tDTS=125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns  by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected.
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written.
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state).
0x1: B_0x1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output.

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state).
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

BKE

Bit 12: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break function disabled
0x1: B_0x1: Break function enabled

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A)..

Allowed values:
0x0: B_0x0: In response to a break 2 event. OC and OCN outputs are disabled
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

BK2F

Bits 20-23: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: No filter, BRK2 acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

BK2E

Bit 24: Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK2 disabled
0x1: B_0x1: Break input BRK2 enabled

BK2P

Bit 25: Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK2 is active low
0x1: B_0x1: Break input BRK2 is active high

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed

BK2DSRM

Bit 27: Break2 Disarm Refer to BKDSRM description.

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode

BK2BID

Bit 29: Break2 bidirectional Refer to BKBID description.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....

Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,

DBL

Bits 8-12: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA..

Allowed values:
0x0: B_0x0: 1 transfer
0x1: B_0x1: 2 transfers
0x2: B_0x2: 3 transfers
0x11: B_0x11: 18 transfers

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-31: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

OR1

option register 1

Offset: 0x50, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCREF_CLR
rw
Toggle Fields.

OCREF_CLR

Bit 0: Ocref_clr source selection This bit selects the ocref_clr input source..

Allowed values:
0x0: B_0x0: COMP1 output is connected to the OCREF_CLR input
0x1: B_0x1: COMP2 output is connected to the OCREF_CLR input

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_3
rw
OC5M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw
OC6M
rw
OC6PE
rw
OC6FE
rw
OC5CE
rw
OC5M
rw
OC5PE
rw
OC5FE
rw
Toggle Fields.

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

CCR5

capture/compare register 4

Offset: 0x58, reset: 0x00000000, access: read-write

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle Fields.

CCR5

Bits 0-15: Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output..

GC5C1

Bit 29: Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..

Allowed values:
0x0: B_0x0: No effect of OC5REF on OC1REFC5
0x1: B_0x1: OC1REFC is the logical AND of OC1REFC and OC5REF

GC5C2

Bit 30: Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..

Allowed values:
0x0: B_0x0: No effect of OC5REF on OC2REFC
0x1: B_0x1: OC2REFC is the logical AND of OC2REFC and OC5REF

GC5C3

Bit 31: Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals..

Allowed values:
0x0: B_0x0: No effect of OC5REF on OC3REFC
0x1: B_0x1: OC3REFC is the logical AND of OC3REFC and OC5REF

CCR6

capture/compare register 4

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle Fields.

CCR6

Bits 0-15: Capture/Compare value.

AF1

DMA address for full transfer

Offset: 0x60, reset: 0x00000001, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x1: B_0x1: BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1)

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x1: B_0x1: COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1)

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x1: B_0x1: COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1)

ETRSEL

Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: ETR legacy mode
0x1: B_0x1: COMP1 output
0x2: B_0x2: COMP2 output
0x3: B_0x3: ADC1 AWD1
0x4: B_0x4: ADC1 AWD2
0x5: B_0x5: ADC1 AWD3

AF2

DMA address for full transfer

Offset: 0x64, reset: 0x00000001, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle Fields.

BK2INE

Bit 0: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN2 input disabled
0x1: B_0x1: BKIN2 input enabled

BK2CMP1E

Bit 1: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled

BK2CMP2E

Bit 2: BRK2 COMP2 enable This bit enables the COMP2 for the timer’s BRK2 input. COMP2 output is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled

BK2INP

Bit 9: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x1: B_0x1: BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x1: B_0x1: COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x1: B_0x1: COMP2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)

TISEL

TIM1 timer input selection register

Offset: 0x68, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw
TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM1_CH1 input
0x1: B_0x1: COMP1 output

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM1_CH2 input
0x1: B_0x1: COMP2 output

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM1_CH3 input

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM1_CH4 input

TIM14

0x40002000: General purpose timers

23/31 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. An UEV is generated by one of the following events:
0x1: B_0x1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set.

URS

Bit 2: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit.

Allowed values:
0x0: B_0x0: Any of the following events generate an UEV if enabled:
0x1: B_0x1: Only counter overflow generates an UEV if enabled.

OPM

Bit 3: One-pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped on the update event
0x1: B_0x1: Counter stops counting on the next update event (clearing the CEN bit).

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),.

Allowed values:
0x0: B_0x0: tDTS = tCK_INT
0x1: B_0x1: tDTS = 2 × tCK_INT
0x2: B_0x2: tDTS = 4 × tCK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled
0x1: B_0x1: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled
0x1: B_0x1: CC1 interrupt enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=’0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.

CC1G

Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NP

Bit 3: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description)..

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: low counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Low Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Low Capture/Compare 1 value.

TISEL

TIM timer input selection register

Offset: 0x68, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM14_CH1 input
0x1: B_0x1: RTC CLK
0x2: B_0x2: HSE/32
0x3: B_0x3: MCO

TIM15

0x40014000: General purpose timers

71/97 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt if enabled

OPM

Bit 3: One-pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the bit CEN)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx).

Allowed values:
0x0: B_0x0: tDTS = tCK_INT
0x1: B_0x1: tDTS = 2*tCK_INT
0x2: B_0x2: tDTS = 4*tCK_INT
0x3: B_0x3: Reserved, do not program this value

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS2
rw
OIS1N
rw
OIS1
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0x0: B_0x0: CCx DMA request sent when CCx event occurs
0x1: B_0x1: CCx DMA requests sent when update event occurs

MMS

Bits 4-6: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:.

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO).
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO).

TI1S

Bit 7: TI1 selection.

Allowed values:
0x0: B_0x0: The TIMx_CH1 pin is connected to TI1 input
0x1: B_0x1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination)

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..

Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..

Allowed values:
0x0: B_0x0: OC1N=0 after a dead-time when MOE=0
0x1: B_0x1: OC1N=1 after a dead-time when MOE=0

OIS2

Bit 10: Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register)..

Allowed values:
0x0: B_0x0: OC2=0 when MOE=0
0x1: B_0x1: OC2=1 when MOE=0

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS1
rw
SMS1
rw
Toggle Fields.

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS1

Bits 4-6: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/slave mode.

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled
0x1: B_0x1: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled
0x1: B_0x1: CC1 interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0x0: B_0x0: CC2 interrupt disabled
0x1: B_0x1: CC2 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0x0: B_0x0: COM interrupt disabled
0x1: B_0x1: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0x0: B_0x0: Trigger interrupt disabled
0x1: B_0x1: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0x0: B_0x0: Break interrupt disabled
0x1: B_0x1: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled
0x1: B_0x1: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0x0: B_0x0: CC1 DMA request disabled
0x1: B_0x1: CC1 DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0x0: B_0x0: CC2 DMA request disabled
0x1: B_0x1: CC2 DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0x0: B_0x0: COM DMA request disabled
0x1: B_0x1: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0x0: B_0x0: Trigger DMA request disabled
0x1: B_0x1: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred

CC2IF

Bit 2: Capture/Compare 2 interrupt flag refer to CC1IF description.

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software..

Allowed values:
0x0: B_0x0: No COM event occurred
0x1: B_0x1: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

Allowed values:
0x0: B_0x0: No trigger event occurred
0x1: B_0x1: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

Allowed values:
0x0: B_0x0: No break event occurred
0x1: B_0x1: An active level has been detected on the break input

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

Allowed values:
0x0: B_0x0: No overcapture has been detected
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

CC2OF

Bit 10: Capture/Compare 2 overcapture flag Refer to CC1OF description.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
rw
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:

CC2G

Bit 2: Capture/Compare 2 generation Refer to CC1G description.

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC2 channel is configured as output
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1N active high
0x1: B_0x1: OC1N active low

CC2E

Bit 4: Capture/Compare 2 output enable Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output polarity Refer to CC1P description.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity Refer to CC1NP description.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields.

CCR2

Bits 0-15: Capture/Compare 2 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

10/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1: B_0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break inputs (BRK and CCS clock failure event) disabled

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if the break input is not be active)

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818)..

Allowed values:
0x0: B_0x0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....

Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....

Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM15 alternate register 1

Offset: 0x60, reset: 0x00000001, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input is active low
0x1: B_0x1: BKIN input is active high

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input is active low
0x1: B_0x1: COMP1 input is active high

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input is active low
0x1: B_0x1: COMP2 input is active high

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM15_CH1 input
0x1: B_0x1: TIM2_IC1
0x2: B_0x2: TIM3_IC1

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM15_CH2 input
0x1: B_0x1: TIM2_IC2
0x2: B_0x2: TIM3_IC2

TIM16

0x40014400: General purpose timers

57/66 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

OPM

Bit 3: One pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the bit CEN)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.

Allowed values:
0x0: B_0x0: tDTS=tCK_INT
0x1: B_0x1: tDTS=2*tCK_INT
0x2: B_0x2: tDTS=4*tCK_INT
0x3: B_0x3: Reserved, do not program this value

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw
OIS1
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0x0: B_0x0: CCx DMA request sent when CCx event occurs
0x1: B_0x1: CCx DMA requests sent when update event occurs

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: OC1N=0 after a dead-time when MOE=0
0x1: B_0x1: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled
0x1: B_0x1: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled
0x1: B_0x1: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0x0: B_0x0: COM interrupt disabled
0x1: B_0x1: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0x0: B_0x0: Break interrupt disabled
0x1: B_0x1: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled
0x1: B_0x1: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0x0: B_0x0: CC1 DMA request disabled
0x1: B_0x1: CC1 DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
BIF
rw
COMIF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software..

Allowed values:
0x0: B_0x0: No COM event occurred
0x1: B_0x1: COM interrupt pending

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

Allowed values:
0x0: B_0x0: No break event occurred
0x1: B_0x1: An active level has been detected on the break input

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

Allowed values:
0x0: B_0x0: No overcapture has been detected
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A capture/compare event is generated on channel 1:

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input.
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..

Allowed values:
0x0: B_0x0: OC1N active high
0x1: B_0x1: OC1N active low

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

10/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1: B_0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break inputs (BRK and CCS clock failure event) disabled

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if the break input is not be active)

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..

Allowed values:
0x0: B_0x0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....

Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM17 option register 1

Offset: 0x60, reset: 0x00000001, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input is active low
0x1: B_0x1: BKIN input is active high

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input is active low
0x1: B_0x1: COMP1 input is active high

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input is active low
0x1: B_0x1: COMP2 input is active high

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM16_CH1 input
0x1: B_0x1: LSI
0x2: B_0x2: LSE
0x3: B_0x3: RTC wakeup

TIM17

0x40014800: General purpose timers

57/66 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

OPM

Bit 3: One pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the bit CEN)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.

Allowed values:
0x0: B_0x0: tDTS=tCK_INT
0x1: B_0x1: tDTS=2*tCK_INT
0x2: B_0x2: tDTS=4*tCK_INT
0x3: B_0x3: Reserved, do not program this value

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw
OIS1
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0x0: B_0x0: CCx DMA request sent when CCx event occurs
0x1: B_0x1: CCx DMA requests sent when update event occurs

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: OC1N=0 after a dead-time when MOE=0
0x1: B_0x1: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled
0x1: B_0x1: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled
0x1: B_0x1: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0x0: B_0x0: COM interrupt disabled
0x1: B_0x1: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0x0: B_0x0: Break interrupt disabled
0x1: B_0x1: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled
0x1: B_0x1: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0x0: B_0x0: CC1 DMA request disabled
0x1: B_0x1: CC1 DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
BIF
rw
COMIF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred

COMIF

Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software..

Allowed values:
0x0: B_0x0: No COM event occurred
0x1: B_0x1: COM interrupt pending

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

Allowed values:
0x0: B_0x0: No break event occurred
0x1: B_0x1: An active level has been detected on the break input

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

Allowed values:
0x0: B_0x0: No overcapture has been detected
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A capture/compare event is generated on channel 1:

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)..

Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input.
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..

Allowed values:
0x0: B_0x0: OC1N active high
0x1: B_0x1: OC1N active low

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

10/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1: B_0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break inputs (BRK and CCS clock failure event) disabled

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if the break input is not be active)

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..

Allowed values:
0x0: B_0x0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....

Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM17 option register 1

Offset: 0x60, reset: 0x00000001, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled

BKCMP1E

Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled

BKCMP2E

Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: BKIN input is active low
0x1: B_0x1: BKIN input is active high

BKCMP1P

Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP1 input is active low
0x1: B_0x1: COMP1 input is active high

BKCMP2P

Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0x0: B_0x0: COMP2 input is active low
0x1: B_0x1: COMP2 input is active high

TISEL

input selection register

Offset: 0x68, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

Allowed values:
0x0: B_0x0: TIM16_CH1 input
0x1: B_0x1: LSI
0x2: B_0x2: LSE
0x3: B_0x3: RTC wakeup

TIM2

0x40000000: General-purpose-timers

51/115 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

OPM

Bit 3: One-pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the bit CEN)

DIR

Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

Allowed values:
0x0: B_0x0: Counter used as upcounter
0x1: B_0x1: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).

Allowed values:
0x0: B_0x0: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1: B_0x1: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2: B_0x2: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3: B_0x3: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.

Allowed values:
0x0: B_0x0: tDTS = tCK_INT
0x1: B_0x1: tDTS = 2 × tCK_INT
0x2: B_0x2: tDTS = 4 × tCK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0x0: B_0x0: CCx DMA request sent when CCx event occurs
0x1: B_0x1: CCx DMA requests sent when update event occurs

MMS

Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO)

TI1S

Bit 7: TI1 selection.

Allowed values:
0x0: B_0x0: The TIMx_CH1 pin is connected to TI1 input
0x1: B_0x1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS1
rw
OCCS
rw
SMS1
rw
Toggle Fields.

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

OCCS

Bit 3: OCREF clear selection This bit is used to select the OCREF clear source.

Allowed values:
0x0: B_0x0: OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1.OCREF_CLR
0x1: B_0x1: OCREF_CLR_INT is connected to ETRF

TS1

Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/Slave mode.

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..

Allowed values:
0x0: B_0x0: Prescaler OFF
0x1: B_0x1: ETRP frequency divided by 2
0x2: B_0x2: ETRP frequency divided by 4
0x3: B_0x3: ETRP frequency divided by 8

ECE

Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

Allowed values:
0x0: B_0x0: External clock mode 2 disabled
0x1: B_0x1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.

Allowed values:
0x0: B_0x0: ETR is non-inverted, active at high level or rising edge
0x1: B_0x1: ETR is inverted, active at low level or falling edge

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled.
0x1: B_0x1: Update interrupt enabled.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled.
0x1: B_0x1: CC1 interrupt enabled.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0x0: B_0x0: CC2 interrupt disabled.
0x1: B_0x1: CC2 interrupt enabled.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0x0: B_0x0: CC3 interrupt disabled.
0x1: B_0x1: CC3 interrupt enabled.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0x0: B_0x0: CC4 interrupt disabled.
0x1: B_0x1: CC4 interrupt enabled.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0x0: B_0x0: Trigger interrupt disabled.
0x1: B_0x1: Trigger interrupt enabled.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled.
0x1: B_0x1: Update DMA request enabled.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0x0: B_0x0: CC1 DMA request disabled.
0x1: B_0x1: CC1 DMA request enabled.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0x0: B_0x0: CC2 DMA request disabled.
0x1: B_0x1: CC2 DMA request enabled.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0x0: B_0x0: CC3 DMA request disabled.
0x1: B_0x1: CC3 DMA request enabled.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0x0: B_0x0: CC4 DMA request disabled.
0x1: B_0x1: CC4 DMA request enabled.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0x0: B_0x0: Trigger DMA request disabled.
0x1: B_0x1: Trigger DMA request enabled.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred

CC2IF

Bit 2: Capture/Compare 2 interrupt flag Refer to CC1IF description.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag Refer to CC1IF description.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag Refer to CC1IF description.

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

Allowed values:
0x0: B_0x0: No trigger event occurred.
0x1: B_0x1: Trigger interrupt pending.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag refer to CC1OF description.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag refer to CC1OF description.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag refer to CC1OF description.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

CC1G

Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:

CC2G

Bit 2: Capture/compare 2 generation Refer to CC1G description.

CC3G

Bit 3: Capture/compare 3 generation Refer to CC1G description.

CC4G

Bit 4: Capture/compare 4 generation Refer to CC1G description.

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

2/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NP

Bit 3: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description..

CC2E

Bit 4: Capture/Compare 2 output enable. Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output Polarity. refer to CC1P description.

CC2NP

Bit 7: Capture/Compare 2 output Polarity. Refer to CC1NP description.

CC3E

Bit 8: Capture/Compare 3 output enable. Refer to CC1E description.

CC3P

Bit 9: Capture/Compare 3 output Polarity. Refer to CC1P description.

CC3NP

Bit 11: Capture/Compare 3 output Polarity. Refer to CC1NP description.

CC4E

Bit 12: Capture/Compare 4 output enable. refer to CC1E description.

CC4P

Bit 13: Capture/Compare 4 output Polarity. Refer to CC1P description.

CC4NP

Bit 15: Capture/Compare 4 output Polarity. Refer to CC1NP description.

CNT_ALTERNATE5

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-30: Most significant part counter value (TIM2) nullLeast significant part of counter value.

UIFCPY

Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-31: High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-31: High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed..

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields.

CCR2

Bits 0-31: High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed..

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle Fields.

CCR3

Bits 0-31: High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed..

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle Fields.

CCR4

Bits 0-31: High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed..

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

Allowed values:
0x0: B_0x0: TIMx_CR1
0x1: B_0x1: TIMx_CR2
0x2: B_0x2: TIMx_SMCR

DBL

Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....

Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM option register

Offset: 0x50, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCREF_CLR
rw
Toggle Fields.

OCREF_CLR

Bit 0: Ocref_clr source selection This bit selects the ocref_clr input source..

Allowed values:
0x0: B_0x0: COMP1 output is connected to the OCREF_CLR input
0x1: B_0x1: COMP2 output is connected to the OCREF_CLR input

AF1

TIM alternate function option register 1

Offset: 0x60, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle Fields.

ETRSEL

Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved.

Allowed values:
0x0: B_0x0: ETR legacy mode
0x1: B_0x1: COMP1
0x2: B_0x2: COMP2
0x3: B_0x3: LSE

TISEL

TIM alternate function option register 1

Offset: 0x68, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.

Allowed values:
0x0: B_0x0: TIM2_CH1 input
0x1: B_0x1: COMP1 output

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.

Allowed values:
0x0: B_0x0: TIM2_CH2 input
0x1: B_0x1: COMP2 output

TIM3

0x40000400: General-purpose-timers

51/115 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

OPM

Bit 3: One-pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the bit CEN)

DIR

Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

Allowed values:
0x0: B_0x0: Counter used as upcounter
0x1: B_0x1: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).

Allowed values:
0x0: B_0x0: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1: B_0x1: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2: B_0x2: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3: B_0x3: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered
0x1: B_0x1: TIMx_ARR register is buffered

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.

Allowed values:
0x0: B_0x0: tDTS = tCK_INT
0x1: B_0x1: tDTS = 2 × tCK_INT
0x2: B_0x2: tDTS = 4 × tCK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0x0: B_0x0: CCx DMA request sent when CCx event occurs
0x1: B_0x1: CCx DMA requests sent when update event occurs

MMS

Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO)

TI1S

Bit 7: TI1 selection.

Allowed values:
0x0: B_0x0: The TIMx_CH1 pin is connected to TI1 input
0x1: B_0x1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS1
rw
OCCS
rw
SMS1
rw
Toggle Fields.

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

OCCS

Bit 3: OCREF clear selection This bit is used to select the OCREF clear source.

Allowed values:
0x0: B_0x0: OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1.OCREF_CLR
0x1: B_0x1: OCREF_CLR_INT is connected to ETRF

TS1

Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/Slave mode.

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..

Allowed values:
0x0: B_0x0: Prescaler OFF
0x1: B_0x1: ETRP frequency divided by 2
0x2: B_0x2: ETRP frequency divided by 4
0x3: B_0x3: ETRP frequency divided by 8

ECE

Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

Allowed values:
0x0: B_0x0: External clock mode 2 disabled
0x1: B_0x1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.

Allowed values:
0x0: B_0x0: ETR is non-inverted, active at high level or rising edge
0x1: B_0x1: ETR is inverted, active at low level or falling edge

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled.
0x1: B_0x1: Update interrupt enabled.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0x0: B_0x0: CC1 interrupt disabled.
0x1: B_0x1: CC1 interrupt enabled.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0x0: B_0x0: CC2 interrupt disabled.
0x1: B_0x1: CC2 interrupt enabled.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0x0: B_0x0: CC3 interrupt disabled.
0x1: B_0x1: CC3 interrupt enabled.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0x0: B_0x0: CC4 interrupt disabled.
0x1: B_0x1: CC4 interrupt enabled.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0x0: B_0x0: Trigger interrupt disabled.
0x1: B_0x1: Trigger interrupt enabled.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled.
0x1: B_0x1: Update DMA request enabled.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0x0: B_0x0: CC1 DMA request disabled.
0x1: B_0x1: CC1 DMA request enabled.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0x0: B_0x0: CC2 DMA request disabled.
0x1: B_0x1: CC2 DMA request enabled.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0x0: B_0x0: CC3 DMA request disabled.
0x1: B_0x1: CC3 DMA request enabled.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0x0: B_0x0: CC4 DMA request disabled.
0x1: B_0x1: CC4 DMA request enabled.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0x0: B_0x0: Trigger DMA request disabled.
0x1: B_0x1: Trigger DMA request enabled.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

CC1IF

Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred

CC2IF

Bit 2: Capture/Compare 2 interrupt flag Refer to CC1IF description.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag Refer to CC1IF description.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag Refer to CC1IF description.

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

Allowed values:
0x0: B_0x0: No trigger event occurred.
0x1: B_0x1: Trigger interrupt pending.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’..

Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag refer to CC1OF description.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag refer to CC1OF description.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag refer to CC1OF description.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

CC1G

Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:

CC2G

Bit 2: Capture/compare 2 generation Refer to CC1G description.

CC3G

Bit 3: Capture/compare 3 generation Refer to CC1G description.

CC4G

Bit 4: Capture/compare 4 generation Refer to CC1G description.

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..

Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

2/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable..

Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..

Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NP

Bit 3: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description..

CC2E

Bit 4: Capture/Compare 2 output enable. Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output Polarity. refer to CC1P description.

CC2NP

Bit 7: Capture/Compare 2 output Polarity. Refer to CC1NP description.

CC3E

Bit 8: Capture/Compare 3 output enable. Refer to CC1E description.

CC3P

Bit 9: Capture/Compare 3 output Polarity. Refer to CC1P description.

CC3NP

Bit 11: Capture/Compare 3 output Polarity. Refer to CC1NP description.

CC4E

Bit 12: Capture/Compare 4 output enable. refer to CC1E description.

CC4P

Bit 13: Capture/Compare 4 output Polarity. Refer to CC1P description.

CC4NP

Bit 15: Capture/Compare 4 output Polarity. Refer to CC1NP description.

CNT_ALTERNATE5

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-30: Most significant part counter value (TIM2) nullLeast significant part of counter value.

UIFCPY

Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-31: High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-31: High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed..

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle Fields.

CCR2

Bits 0-31: High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed..

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle Fields.

CCR3

Bits 0-31: High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed..

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle Fields.

CCR4

Bits 0-31: High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed..

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

Allowed values:
0x0: B_0x0: TIMx_CR1
0x1: B_0x1: TIMx_CR2
0x2: B_0x2: TIMx_SMCR

DBL

Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....

Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM option register

Offset: 0x50, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCREF_CLR
rw
Toggle Fields.

OCREF_CLR

Bit 0: Ocref_clr source selection This bit selects the ocref_clr input source..

Allowed values:
0x0: B_0x0: COMP1 output is connected to the OCREF_CLR input
0x1: B_0x1: COMP2 output is connected to the OCREF_CLR input

AF1

TIM alternate function option register 1

Offset: 0x60, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle Fields.

ETRSEL

Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved.

Allowed values:
0x0: B_0x0: ETR legacy mode
0x1: B_0x1: COMP1
0x2: B_0x2: COMP2
0x3: B_0x3: LSE

TISEL

TIM alternate function option register 1

Offset: 0x68, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle Fields.

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.

Allowed values:
0x0: B_0x0: TIM2_CH1 input
0x1: B_0x1: COMP1 output

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.

Allowed values:
0x0: B_0x0: TIM2_CH2 input
0x1: B_0x1: COMP2 output

TIM6

0x40001000: Basic timers

12/15 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

OPM

Bit 3: One-pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the CEN bit).

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered.
0x1: B_0x1: TIMx_ARR register is buffered.

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled.
0x1: B_0x1: Update interrupt enabled.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled.
0x1: B_0x1: Update DMA request enabled.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Counter value.

UIFCPY

Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Prescaler value.

TIM7

0x40001400: Basic timers

12/15 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

Allowed values:
0x0: B_0x0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

OPM

Bit 3: One-pulse mode.

Allowed values:
0x0: B_0x0: Counter is not stopped at update event
0x1: B_0x1: Counter stops counting at the next update event (clearing the CEN bit).

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0x0: B_0x0: TIMx_ARR register is not buffered.
0x1: B_0x1: TIMx_ARR register is buffered.

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0x0: B_0x0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
0x1: B_0x1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0x0: B_0x0: Update interrupt disabled.
0x1: B_0x1: Update interrupt enabled.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0x0: B_0x0: Update DMA request disabled.
0x1: B_0x1: Update DMA request enabled.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..

Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Counter value.

UIFCPY

Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Prescaler value.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

136/170 fields covered. Toggle Registers.

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

18/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver is disabled
0x1: B_0x1: Receiver is enabled and begins searching for a start bit

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TC = 1 in the USART_ISR register

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TXE =1 in the USART_ISR register

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever PE = 1 in the USART_ISR register

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Idle line
0x1: B_0x1: Address mark

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

Allowed values:
0x0: B_0x0: Oversampling by 16
0x1: B_0x1: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

19/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Slave mode disabled.
0x1: B_0x1: Slave mode enabled.

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: 1 stop bit
0x1: B_0x1: 0.5 stop bit.
0x2: B_0x2: 2 stop bits
0x3: B_0x3: 1.5 stop bits

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Half duplex mode is not selected
0x1: B_0x1: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for reception
0x0: B_0x0: DMA mode is disabled for reception

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for transmission
0x0: B_0x0: DMA mode is disabled for transmission

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE  =  1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: nCTS line set
0x1: B_0x1: nCTS line reset

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCBGTCF
w
TCCF
w
TXFECF
w
IDLECF
w
ORECF
w
NECF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

136/170 fields covered. Toggle Registers.

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

18/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver is disabled
0x1: B_0x1: Receiver is enabled and begins searching for a start bit

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TC = 1 in the USART_ISR register

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TXE =1 in the USART_ISR register

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever PE = 1 in the USART_ISR register

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Idle line
0x1: B_0x1: Address mark

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

Allowed values:
0x0: B_0x0: Oversampling by 16
0x1: B_0x1: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

19/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Slave mode disabled.
0x1: B_0x1: Slave mode enabled.

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: 1 stop bit
0x1: B_0x1: 0.5 stop bit.
0x2: B_0x2: 2 stop bits
0x3: B_0x3: 1.5 stop bits

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Half duplex mode is not selected
0x1: B_0x1: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for reception
0x0: B_0x0: DMA mode is disabled for reception

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for transmission
0x0: B_0x0: DMA mode is disabled for transmission

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE  =  1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: nCTS line set
0x1: B_0x1: nCTS line reset

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCBGTCF
w
TCCF
w
TXFECF
w
IDLECF
w
ORECF
w
NECF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

136/170 fields covered. Toggle Registers.

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

18/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver is disabled
0x1: B_0x1: Receiver is enabled and begins searching for a start bit

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TC = 1 in the USART_ISR register

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TXE =1 in the USART_ISR register

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever PE = 1 in the USART_ISR register

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Idle line
0x1: B_0x1: Address mark

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

Allowed values:
0x0: B_0x0: Oversampling by 16
0x1: B_0x1: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

19/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Slave mode disabled.
0x1: B_0x1: Slave mode enabled.

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: 1 stop bit
0x1: B_0x1: 0.5 stop bit.
0x2: B_0x2: 2 stop bits
0x3: B_0x3: 1.5 stop bits

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Half duplex mode is not selected
0x1: B_0x1: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for reception
0x0: B_0x0: DMA mode is disabled for reception

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for transmission
0x0: B_0x0: DMA mode is disabled for transmission

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE  =  1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: nCTS line set
0x1: B_0x1: nCTS line reset

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCBGTCF
w
TCCF
w
TXFECF
w
IDLECF
w
ORECF
w
NECF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256

USART4

0x40004C00: Universal synchronous asynchronous receiver transmitter

136/170 fields covered. Toggle Registers.

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

18/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver is disabled
0x1: B_0x1: Receiver is enabled and begins searching for a start bit

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TC = 1 in the USART_ISR register

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TXE =1 in the USART_ISR register

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever PE = 1 in the USART_ISR register

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Idle line
0x1: B_0x1: Address mark

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

Allowed values:
0x0: B_0x0: Oversampling by 16
0x1: B_0x1: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

19/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Slave mode disabled.
0x1: B_0x1: Slave mode enabled.

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: 1 stop bit
0x1: B_0x1: 0.5 stop bit.
0x2: B_0x2: 2 stop bits
0x3: B_0x3: 1.5 stop bits

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Half duplex mode is not selected
0x1: B_0x1: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for reception
0x0: B_0x0: DMA mode is disabled for reception

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for transmission
0x0: B_0x0: DMA mode is disabled for transmission

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE  =  1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: nCTS line set
0x1: B_0x1: nCTS line reset

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCBGTCF
w
TCCF
w
TXFECF
w
IDLECF
w
ORECF
w
NECF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256

USART5

0x40005000: Universal synchronous asynchronous receiver transmitter

136/170 fields covered. Toggle Registers.

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

18/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver is disabled
0x1: B_0x1: Receiver is enabled and begins searching for a start bit

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TC = 1 in the USART_ISR register

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TXE =1 in the USART_ISR register

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever PE = 1 in the USART_ISR register

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Idle line
0x1: B_0x1: Address mark

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

Allowed values:
0x0: B_0x0: Oversampling by 16
0x1: B_0x1: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

19/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Slave mode disabled.
0x1: B_0x1: Slave mode enabled.

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: 1 stop bit
0x1: B_0x1: 0.5 stop bit.
0x2: B_0x2: 2 stop bits
0x3: B_0x3: 1.5 stop bits

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Half duplex mode is not selected
0x1: B_0x1: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for reception
0x0: B_0x0: DMA mode is disabled for reception

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for transmission
0x0: B_0x0: DMA mode is disabled for transmission

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE  =  1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: nCTS line set
0x1: B_0x1: nCTS line reset

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCBGTCF
w
TCCF
w
TXFECF
w
IDLECF
w
ORECF
w
NECF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256

USART6

0x40013C00: Universal synchronous asynchronous receiver transmitter

136/170 fields covered. Toggle Registers.

CR1_FIFO_DISABLED

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

18/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..

Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver is disabled
0x1: B_0x1: Receiver is enabled and begins searching for a start bit

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever IDLE = 1 in the USART_ISR register

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TC = 1 in the USART_ISR register

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TXE =1 in the USART_ISR register

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever PE = 1 in the USART_ISR register

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Idle line
0x1: B_0x1: Address mark

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the CMF bit is set in the USART_ISR register.

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

Allowed values:
0x0: B_0x0: Oversampling by 16
0x1: B_0x1: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

19/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Slave mode disabled.
0x1: B_0x1: Slave mode enabled.

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window

CLKEN

Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: 1 stop bit
0x1: B_0x1: 0.5 stop bit.
0x2: B_0x2: 2 stop bits
0x3: B_0x3: 1.5 stop bits

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.

ADD

Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE = 0)..

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Half duplex mode is not selected
0x1: B_0x1: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for reception
0x0: B_0x0: DMA mode is disabled for reception

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

Allowed values:
0x1: B_0x1: DMA mode is enabled for transmission
0x0: B_0x0: DMA mode is disabled for transmission

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: USART baud rate.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to ..

Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_FIFO_DISABLED

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..

Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE  =  1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..

Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: nCTS line set
0x1: B_0x1: nCTS line reset

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835..

Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCBGTCF
w
TCCF
w
TXFECF
w
IDLECF
w
ORECF
w
NECF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256

VREFBUF

0x40010030: System configuration controller

4/5 fields covered. Toggle Registers.

VREFBUF_CSR

VREFBUF control and status register

Offset: 0x0, reset: 0x00000002, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r
VRS
rw
HIZ
rw
ENVR
rw
Toggle Fields.

ENVR

Bit 0: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode..

Allowed values:
0x0: B_0x0: Internal voltage reference mode disable (external voltage reference mode).
0x1: B_0x1: Internal voltage reference mode (reference buffer enable or hold mode) enable.

HIZ

Bit 1: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration..

Allowed values:
0x0: B_0x0: VREF+ pin is internally connected to the voltage reference buffer output.
0x1: B_0x1: VREF+ pin is high impedance.

VRS

Bit 2: Voltage reference scale This bit selects the value generated by the voltage reference buffer..

Allowed values:
0x0: B_0x0: Voltage reference set to VREF_OUT1 (around 2.048 V).
0x1: B_0x1: Voltage reference set to VREF_OUT2 (around 2.5 V).

VRR

Bit 3: Voltage reference buffer ready.

Allowed values:
0x0: B_0x0: the voltage reference buffer output is not ready.
0x1: B_0x1: the voltage reference buffer output reached the requested level.

VREFBUF_CCR

VREFBUF calibration control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle Fields.

TRIM

Bits 0-5: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows the tuning of the internal reference buffer voltage..

WWDG

0x40002C00: System window watchdog

2/6 fields covered. Toggle Registers.

WWDG_CR

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw
T
rw
Toggle Fields.

T

Bits 0-6: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)..

WDGA

Bit 7: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset..

Allowed values:
0x0: B_0x0: Watchdog disabled
0x1: B_0x1: Watchdog enabled

WWDG_CFR

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTB
rw
EWI
rw
W
rw
Toggle Fields.

W

Bits 0-6: 7-bit window value These bits contain the window value to be compared with the down-counter..

EWI

Bit 9: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset..

WDGTB

Bits 11-13: Timer base The timebase of the prescaler can be modified as follows:.

Allowed values:
0x0: B_0x0: CK Counter Clock (PCLK div 4096) div 1
0x1: B_0x1: CK Counter Clock (PCLK div 4096) div 2
0x2: B_0x2: CK Counter Clock (PCLK div 4096) div 4
0x3: B_0x3: CK Counter Clock (PCLK div 4096) div 8
0x4: B_0x4: CK Counter Clock (PCLK div 4096) div 16
0x5: B_0x5: CK Counter Clock (PCLK div 4096) div 32
0x6: B_0x6: CK Counter Clock (PCLK div 4096) div 64
0x7: B_0x7: CK Counter Clock (PCLK div 4096) div 128

WWDG_SR

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.